Oral presentation

[10p-S223-1~11] 11.5 Junction and circuit fabrication process, digital applications

Sun. Mar 10, 2019 1:45 PM - 4:45 PM S223 (S223)

Shigeyuki Miyajima(NICT), Yuki Yamanashi(Yokohama National Univ.)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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1:45 PM - 2:00 PM

[10p-S223-1] [Young Scientist Presentation Award Speech] Demonstration of a D-latch using reversible quantum-flux-parametron logic

〇Taiki Yamae¹, Naoki Takeuchi^2,3, Yuki Yamanashi^1,2, Nobuyuki Yoshikawa^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ., 3.JST-PRESTO)

2:00 PM - 2:15 PM

[10p-S223-2] Operation analysis for the realization of matrix memory driven by SFQ Pulses

〇Yuto Takeshita¹, Tomohiro Kamiya¹, Kyosuke Sano¹, Masamitsu Tanaka¹, Taro Yamashita^1,2, Akira Fujimaki¹ (1.Nagoya Univ., 2.JST PRESTO)

2:15 PM - 2:30 PM

△ [10p-S223-3] Design and Evaluation of a 32-word by 1-bit Resister File Using Adiabatic Quantum Flux Parametron Logic

〇(M1)Tomohiro Tamura¹, Naoki Takeuchi^2,3, Christopher Ayala², Yuki Yamanashi^1,2, Nobuyuki Yoshikawa^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Nat'l Univ., 2.IAS, Yokohama Nat'l Univ., 3.JST-PRESTO)

2:30 PM - 2:45 PM

△ [10p-S223-4] Design and Evaluation of a Five-Input Majority Gate using Adiabatic Quantum Flux Parametron Logic

〇(B)Yuichi Yamazaki¹, Yamae Taiki¹, Takeuchi Naoki^2,3, Yuki Yamanashi^1,2, Nobuyuki Yoshikawa^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ., 3.JST-PRESTO)

2:45 PM - 3:00 PM

[10p-S223-5] Design and Evaluation of Arbitrary Output Logic Gate by Superconducting Neural Network Using Quantum Flux Parametron

〇(B)Daiki Yamaguchi¹, Yuki Yamanashi^1,2, Naoki Takeuchi², Nobuyuki Yoshikawa^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ.)

3:00 PM - 3:15 PM

[10p-S223-6] Evaluation of Bit Error Rate of AQFP logic considering a thermal noise

〇Daiki Ito¹, Naoki Takeuchi^2,3, Yuki Yamanashi^1,2, Nobuyuki Yoshikawa^1,2 (1.Yokohama Nat Univ., 2.IAS, Yokohama Nat. Univ., 3.JST-PRESTO)

3:30 PM - 3:45 PM

[10p-S223-7] Study on superconducting nano-structured line drivers for 1-Gb Josephson-CMOS hybrid memory

〇Kyosuke Sano¹, Kohei Maruyama¹, Masamitsu Tanaka¹, Taro Yamashita^1,2, Masumi Inoue³, Akira Fujimaki¹ (1.Nagoya Univ., 2.JST-PREST, 3.Meijo Univ.)

3:45 PM - 4:00 PM

[10p-S223-8] Design and evaluation of single flux quantum circuits using local flux bias

〇Shunta Asada¹, Yuki Yamanashi¹, Nobuyuki Yoshikawa¹ (1.Yokohama Natl. Univ.)

4:00 PM - 4:15 PM

[10p-S223-9] Fractional flux vortices in a Nb based artificial multi-band superconductor

〇Hirotake Yamamori¹, Yasumoto Tanaka¹, Syunichi Arisawa², Taichiro Nisio³, Takashi Yanagisawa¹ (1.AIST, 2.NIMS, 3.TUS)

4:15 PM - 4:30 PM

[10p-S223-10] Characterization of barrier thickness dependence of critical current density in ferromagnetic Josephson junctions for superconducting qubit

〇Haruki Kato¹, Tomohiro Kamiya¹, Sunmi Kim², Wei Qiu², Hirotaka Terai², Kouichi Semba², Taro Yamashita^1,3, Akira Fujimaki¹ (1.Nagoya Univ., 2.NICT, 3.JST-PRESTO)

4:30 PM - 4:45 PM

[10p-S223-11] Study on fabrication process of magnetic Josephson junctions on Nb 4-layer superconductiong integrated circuits

〇Daiki Hasegawa¹, Yuto Takeshita¹, Tomohiro Kamiya¹, Kyosuke Sano¹, Masamitsu Tanaka¹, Taro Yamashita^1,2, Akira Fujimaki¹ (1.Nagoya Univ., 2.JST-PRESTO)

Sessions

11 Superconductivity » 11.5 Junction and circuit fabrication process, digital applications