Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

[16p-B10-1~12] 13.4 Si wafer processing /Si based thin film /MEMS/Integration technology

Fri. Sep 16, 2016 1:45 PM - 5:00 PM B10 (Exhibition Hall)

Minoru Sasaki(Toyota Tech. Inst.), Kuniyuki Kakushima(Titech)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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1:45 PM - 2:00 PM

[16p-B10-1] Development and Characterization of Process Cutting Half-inch Wafers off a Large Wafer

〇Norio Umeyama^1,2, Takaaki Sakai³, Atsushi Kajikura³, Kouichiro Ichikawa³, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.Fujikoshi Machinery)

2:00 PM - 2:15 PM

[16p-B10-2] Effect of thermal convection on the Minimal Si-CVD equipment (II)

〇Yuuki Ishida^1,2, Takanori Mikahara^1,2, Noriko Miura², Takahiro Ito³, Shinichi Ikeda^1,2, Hitoshi Habuka⁴, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.ORIENTAL MOTER Co, 4.YNU)

2:15 PM - 2:30 PM

[16p-B10-3] Transport Phenomena for Silicon Epitaxy in Minimal CVD Reactor

〇Miya Matsuo¹, Hitoshi Habuka¹, Ayami Yamada¹, Ning Li¹, Takanori Mikahara², Shin-ichi Ikeda^2,3, Yuuki Ishida^2,3, Shiro Hara^2,3 (1.Yokohama Nat. Univ., 2.MINIMAL, 3.AIST)

2:30 PM - 2:45 PM

[16p-B10-4] Half-Inch Silicon CVD Reactor Using Concentrated Infrared Light Heater (7)

〇NING LI¹, MIYA MATSUO¹, HITOSHI HABUKA¹, TAKANORI MIKAHARA², SHIN-ICHI IKEDA^2,3, YUUKI ISHIDA^2,3, SHIRO HARA^2,3 (1.Yokohama National Univ., 2.MINIMAL, 3.AIST)

2:45 PM - 3:00 PM

[16p-B10-5] Techniques to improve the resist plane uniformity within the half-inch wafer by minimal coater

〇Hiroyuki Tanaka^1,2, Takuya Koga², Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

3:00 PM - 3:15 PM

△ [16p-B10-6] Investigations of the Mechanism of Photoresist Removal in Water Plasma Ashing

〇TAKUYA KITANO¹, HIROAKI SUZUKI¹, ARUFUA SHIOTA¹, TATSUO ISHIJIMA¹, YASUNORI TANAKA¹, YOSHIHIKO UESUGI¹, SOMMAWAN KHUMPUANG^2,3, SHIRO HARA^2,3 (1.Kanazawa Univ., 2.MINIMAL, 3.AIST)

3:30 PM - 3:45 PM

[16p-B10-7] Through silicon via etching with high-speed gas-switching Bosch process using minimal ICP deep trench etcher

〇Hiroyuki Tanaka^1,2, Hisato Ogiso^1,2, Shizuka Nakano^1,2, Toshihiro Hayami³, Toshiya Miyazaki³, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.SPPT)

3:45 PM - 4:00 PM

[16p-B10-8] Electrical Characteristics of Gate Thermal Oxide Processed by Minimal Focused Light Heating Furnace

〇Noriko Miura¹, Fumito Imura^1,2, Takeshi Yamada^1,3, Takeshi Aizawa^1,3, Shinichi Ikeda^1,2, Yuuki Ishida^1,2, Takanori Mikahara^1,2, Yasuhiro Onishi^1,3, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.MINIMAL, 2.AIST, 3.YONEKURA)

4:00 PM - 4:15 PM

[16p-B10-9] Characterization of p-MOS formed using the minimal furnace that irradiates a wafer with laser from the backside

〇kazushige sato¹, takashi chiba^1,3, masao terada^1,3, ikeda shinichi^1,2, Sommawan Khumpuang^1,2, shiro hara^1,2 (1.Minimal Fab Development Association, 2.AIST, 3.Sakaguchi E.H VOC Corp.)

4:15 PM - 4:30 PM

[16p-B10-10] CMOSFET Fabrication by Minimal Spin-on Dopant Process using Plasma Enhanced CVD TEOS as Thermal diffusion mask

〇Kazuhiro Koga^1,2, Fumito Imura^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

4:30 PM - 4:45 PM

[16p-B10-11] Investigation of Effective Carrier Mobility in Minimal SOI-MOSFETs

〇Yongxun Liu¹, Sommawan Khumpuang¹, Masayoshi Nagao¹, Takashi Matsukawa¹, Shiro Hara¹ (1.AIST)

4:45 PM - 5:00 PM

[16p-B10-12] Fabrication of Half-Inch Size Package by Minimal Fab

〇Fumito Imura^1,2, Michihiro Inoue¹, Arami Saruwatari^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.Minimal Fab)

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