Oral presentation

13 Semiconductors » 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

[21p-233-1~14] 13.4 Si wafer processing /Si based thin film /Interconnect technology/ MEMS/ Integration technology

Fri. Sep 21, 2018 1:00 PM - 4:45 PM 233 (233)

Kuniyuki Kakushima(Tokyo Tech), Yan Wu(Nihon University)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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1:00 PM - 1:15 PM

[21p-233-1] Evaluation of the electrical characteristics of thermal oxide film formed by changing the heating profile by a minimal laser heating furnace

〇kazushige sato^1,3, Takashi Chiba^1,3, Masao Terada^1,3, Shinichi Ikeda^1,2, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.MINIMAL, 2.AIST, 3.Sakaguchi E.H VOC Corp.)

1:15 PM - 1:30 PM

[21p-233-2] Development of Minimal Ion Implantation Tool

〇Noriko Miura¹, Naoki Hashimoto^1,2, Yoshitaka Kitamura^1,2, Fumito Imura^1,3, Kazushige Sato¹, Kazuhiro Koga¹, Yuuki Ishida^1,3, Toshiyuki Oodaira^1,3, Sommawan Khumpuang^1,3, Shiro Hara^1,3 (1.MINIMAL, 2.FUJI IMVAC, 3.AIST)

1:30 PM - 1:45 PM

[21p-233-3] TiN-Gate SOI CMOS Fabricated by minimal fab

〇Kazuhiro Koga¹, Y. X. Liu², Fumito Imura^1,2, Masashi Kase², Shuichi Noda², Kazumasa Nemoto², Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.MINIMAL, 2.AIST)

1:45 PM - 2:00 PM

[21p-233-4] Fabrication of 2-input NAND gate by Minimal TiN SOI-CMOS process

〇Koichi Morikawa¹, Kozo Takeuchi¹, Yasushi Igarashi¹, Hiroyuki Shindo¹, Somawan Khumpuang², Shiro Hara² (1.JAXA, 2.AIST)

2:00 PM - 2:15 PM

[21p-233-5] Measurement and evaluation of pMOS current mirror circuits fabricated by Minimalfab

〇Tomoaki Kageyama^1,2, Sommawan Khumpuang^2,3, Shiro Hara^2,3, Sang-Seok Lee¹ (1.Tottori Univ., 2.AIST, 3.MINIMAL)

2:15 PM - 2:30 PM

[21p-233-6] Development and Characterization of Minimal Plasma tool for Metal Etching(２)

〇Masashi Kase¹, Hiroyuki Tanaka^1,3, Yoshiyuki Nozawa^2,3, Toshiyasu Hayami^2,3, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.SPP Technologies)

2:30 PM - 2:45 PM

[21p-233-7] Techniques to improve the grooved pattern through silicon via etching process with minimal ICP deep trench etcher

〇Hiroyuki Tanaka^1,2, Hisato Ogiso^1,2, Shizuka Nakano^1,2, Yoshiyuki Nozawa^2,3, Toshihiro Hayami^2,3, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.SPPT)

2:45 PM - 3:00 PM

[21p-233-8] Die-Bonding Process of Half-Inch Wafer for Uniformizing of Laser-Vias

〇Fumito Imura^1,2, Seiji Iwasaki³, Hiroshi Matsushita³, Michihiro Inoue¹, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL, 3.ISHII TOOL&ENG.)

3:15 PM - 3:30 PM

[21p-233-9] Development of CMOS-MEMS Co-Integrated Devices Using Minimal-Fab Process

〇Yongxun Liu¹, Hiroyuki Tanaka^1,2, Kazuhiro Koga², Sommawan Khumpuang^1,2, Masayoshi Nagao¹, Takashi Matsukawa¹, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

3:30 PM - 3:45 PM

[21p-233-10] Microneedle array fabrication using thick half-inch wafer

〇Sommawan Khumpuang^1,2, Kazumasa Nemoto^1,2, Hiroyuki Tanaka^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

3:45 PM - 4:00 PM

[21p-233-11] Characterization of CMP within wafer non-uniformity

〇Harumi Iitsuka^1,2, Takashi Yajima^3,2, Noriko Miura², Sommawan Khumpuang^2,3, Shiro Hara^2,3 (1.Yokogawa SS, 2.Minimal, 3.AIST)

4:00 PM - 4:15 PM

[21p-233-12] Fabrication of simple multi water quality sensors by Minimal Fab

〇Tomoaki Kageyama^1,2, Sommawan Khumpuang^2,3, Shiro Hara^2,3, Sang-Seok Lee¹ (1.Tottori Univ., 2.AIST, 3.MINIMAL)

4:15 PM - 4:30 PM

[21p-233-13] Solder Ball Joints in Half-Inch Sized BGA Package

〇Fumito Imura^1,2, Michihiro Inoue¹, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

4:30 PM - 4:45 PM

[21p-233-14] Cleanroom-Free Environment-Control System PLAD for Minimal fab (II)

〇Takashi Yajima^1,2, Masaharu Yasui^1,2, Noriko Miura², Sommawan Khumpuang^1,2, Hitoshi Maekawa^1,2, Shiro Hara^1,2 (1.AIST, 2.MINIMAL)

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