Oral presentation

[20p-C213-1~14] 11.5 Junction and circuit fabrication process, digital applications

Fri. Sep 20, 2019 1:15 PM - 5:00 PM C213 (C213)

Yoshinao Mizugaki(UEC), Yuki Yamanashi(Yokohama Natl. Univ.)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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1:15 PM - 1:30 PM

△ [20p-C213-1] Study of a microwave switch with controllable amplitude using single flux quantum circuits for quantum computers

〇Shiori Michibayashi¹, Naoki Takeuchi², Yuki Yamanashi^1,2, Nobuyuki Yoshikawa^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ.)

1:30 PM - 1:45 PM

△ [20p-C213-2] Fabrication of magnetic Josephson junctions on Nb 4-layer superconducting integrated circuits

〇Daiki Hasegawa¹, Yuto Takeshita¹, Kyosuke Sano¹, Masamitsu Tanaka¹, Taro Yamashita^1,2, Akira Fujimaki¹ (1.Nagoya Univ., 2.JST-PRESTO)

1:45 PM - 2:00 PM

△ [20p-C213-3] Design of the Interface between Adiabatic Quantum Flux Parametron Circuits and Single Flux Quantum Circuits

〇(M1)Yuichi Yamazaki¹, Taiki Yamae¹, Naoki Takeuchi², Yuichi Yamazaki^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ.)

2:00 PM - 2:15 PM

△ [20p-C213-4] Bit Extension of a 32-word Resister File Using Adiabatic Quantum Flux Parametron Logic

〇Tomohiro Tamura¹, Naoki Takeuchi², Christopher Ayala², Yuki Yamanashi^1,2, Nobuyuki Yoshikawa^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ.)

2:15 PM - 2:30 PM

[20p-C213-5] Fabrication of SQUIDs with a period of half flux quantum in magnetic modulation pattern

〇Yuto Takeshita¹, Daiki Hasegawa¹, Tomohiro Kamiya¹, Kyosuke Sano¹, Masamitsu Tanaka¹, Taro Yamashita^1,2, Akira Fujimaki¹ (1.Nagoya Univ., 2.JST PRESTO)

2:30 PM - 2:45 PM

[20p-C213-6] Demonstration of an 8-word by 1-bit register file using reversible quantum-flux-parametron logic

〇Taiki Yamae¹, Naoki Takeuchi², Nobuyuki Yoshikawa^1,2 (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ.)

2:45 PM - 3:00 PM

[20p-C213-7] Evaluation of Bit Error Rate of Adiabatic Quantum Flux Parametron Circuits Considering Gate-to-Gate Interconnection

〇(M1)Daiki Ito¹, Naoki Takeuchi², Yuki Yamanashi^1,2, Nobuyuki Yoshikawa^1,2 (1.Yokohama Natl. Univ., 2.IAS, Yokohama Natl. Univ.)

3:00 PM - 3:15 PM

[20p-C213-8] Analysis and evaluation of influence of 1/f noises on operation stability of superconducting circuit

〇Yusuke Tsuna¹, Yuki Yamanashi¹, Nobuyuki Yoshikawa¹ (1.Yokohama Natl. Univ.)

3:30 PM - 3:45 PM

[20p-C213-9] Low-latency operation of adiabatic quantum-flux-parametron using delay-line clocking

〇Naoki Takeuchi¹, Yuxing He¹, Nobuyuki Yoshikawa¹ (1.Yokohama Natl. Univ.)

3:45 PM - 4:00 PM

[20p-C213-10] Design and error-rate testing of an area-reduced SFQ-NOT gate

〇Koki Yamazaki¹, Hiroshi Shimada¹, Yoshinao Mizugaki¹ (1.Univ. of Electro-Comm.)

4:00 PM - 4:15 PM

[20p-C213-11] Design of single flux quantum memory cell capable of being data input by applying magnetic flux externally and its application to look up table

〇(M1)Takuya Hosoya¹, Yuki Yamanashi¹, Nobuyuki Yoshikawa¹ (1.Dept. of Electrical and Computer Eng., Yokohama Natl. Univ.)

4:15 PM - 4:30 PM

[20p-C213-12] Study on integrated processes for SFQ circuits and superconducting nano-devices

〇Naoki Kondo¹, Kyosuke sano¹, Tanaka Masamitu¹, Taro Yamashita^1,3, Masumi Inoue², Akira Fujimaki¹ (1.Nagoya Univ., 2.Meijo Univ., 3.JST-PRESTO)

4:30 PM - 4:45 PM

[20p-C213-13] Development of a single flux quantum-based signal processor for a photon-number-resolving system by using superconducting nanowire single photon detectors

〇Shigeyuki Miyajima¹, Fumihiro China¹, Masahiro Yabuno¹, Shigehito Miki^1,2, Hirotaka Terai¹ (1.NICT, 2.Kobe Univ.)

4:45 PM - 5:00 PM

[20p-C213-14] Double-Flux-Quantum Amplifiers with magnetically-coupled parallel input terminals

〇Yuta Somei¹, Koki Yamazaki¹, Higuchi Komei¹, Hiroshi Shimada¹, Yoshinao Mizugaki¹ (1.UEC Tokyo)

Sessions

11 Superconductivity » 11.5 Junction and circuit fabrication process, digital applications