[PS-3-09] Numerical Design for Power Integrity Analysis of Tunnel Field Effect Transistors

^○C. Tanaka¹, T. Tanamoto¹, M. Koyama¹ (1.Toshiba Corp. (Japan))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 11:51 〜 11:53 |PDF ダウンロード

[PS-3-10] Effects of Si Recess Structure on Performance and Reliability in High Voltage n-MOSFETs

C. -Y. Chen¹, J. F. Chen¹,^○Y. -L. Tsai¹, H. -T. Hsu², H. -P. Hwang² (1.National Cheng Kung Univ. (Taiwan), 2.Powerchip Tech. Corp. (Taiwan))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 11:53 〜 11:55 |PDF ダウンロード

[PS-3-11] Theoretical Investigation of the Performance Improvement in GeSn/SiGeSn hetero Line Tunneling FET (HL-TFET)

^○H. Wang¹, G. Han¹, Y. Liu¹, C. Zhang¹, J. Zhang¹, Y. Hao¹ (1.Xidian Univ. (China))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 11:55 〜 11:57 |PDF ダウンロード

[PS-3-12] Ge-cap Quantum Well Bulk FinFET for 5nm node CMOS Integration

^○E. D. Kurniawan^1,2, S. -Y. Yang¹, Y. -Y. Yang¹, K. -H. Peng¹, V. Thirunavukkarasu^1,2, Y. -H. Lin³, Y. -C. Wu¹ (1.National Tsing Hua Univ. (Taiwan), 2.Academia Sinica (Taiwan), 3.National United Univ. (Taiwan))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 11:57 〜 11:59 |PDF ダウンロード

[PS-3-13 (Late News)] Hot-carrier Induced Drastic Off-state Leakage Current Degradation in STI-based N-channel LDMOS

^○K. Takahashi¹, K. Komatsu¹, T. Sakamoto¹, K. Kimura¹, F. Matsuoka¹ (1.Toshiba Electronic Devices & Storage Corp. (Japan))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 11:59 〜 12:01 |PDF ダウンロード

[PS-3-14 (Late News)] TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation

^○K. Kukita¹, T. Uechi¹, J. Shimokawa¹, M. Goto¹, Y. Yokota¹, S. Kawanaka¹, T. Tanamoto², M. Koyama², H. Tanimoto¹, S. Takagi³ (1.Toshiba Memory Corp. (Japan), 2.Toshiba Corp. (Japan), 3.Univ. of Tokyo (Japan))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 12:01 〜 12:03 |PDF ダウンロード

[PS-3-15 (Late News)] Multi-V_T with Metal Gate Work-function Modulation by PLAD Implants for Ge FinFET Applications

^○S. D. Kothari¹, H. Nejad², N. Variam², S. Lodha¹ (1.Indian Inst. of Tech. Bombay (India), 2.Applied Materials Inc. (USA))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 12:03 〜 12:05 |PDF ダウンロード

[PS-3-16 (Late News)] Low-Temperature Microwave Annealing Process for In_0.53Ga_0.47As MOSFETs

^○J. W. Lin¹, Q. -H. Luc¹, K. S. Yang¹, C. -C. Chang¹, C. -C. Fan Chiang¹, H. B. Do¹, H. M. T. Ha¹, S. H. Huynh¹, Y. D. Jin¹, T. A. Nguyen¹, Y. -C. Lin¹, E. Y. Chang¹ (1.National Chiao Tung Univ. (Taiwan))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 12:05 〜 12:07 |PDF ダウンロード

[PS-4-01] Resistive Switching in V₂O₃ Thin Films Induced by Current Sweeps and Voltage Pulses

^○M. Menghini¹, P. Homm¹, C. Vets¹, B. Van Bilzen¹, J. P. Locquet¹ (1.KU Leuven (Belgium))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 11:35 〜 11:37 |PDF ダウンロード

[PS-4-02] Non-Destructive Observation of Chemical State in ReRAM by Laser-excited Photoemission Electron Microscopy

^○J. Kawakita^1,2, H. Shima^2,3, Y. Naitoh^2,3, H. Akinaga^2,3, T. Taniuchi^1,2, S. Shin^1,2 (1.Univ. of Tokyo (Japan), 2.AIST-UTokyo Advanced Operando-Measurement Tech. Open Innovation Lab. (OPERANDO-OIL) (Japan), 3.AIST (Japan))

2017 International Conference on Solid State Devices and Materials |2017年9月21日(木) 11:37 〜 11:39 |PDF ダウンロード