2017 International Conference on Solid State Devices and Materials

2017年9月19日〜 2017年9月22日
Sendai International Center

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763件中(571 - 580)

[PS-3-05] Short Channel Modeling of Tunnel FET's

^○K. Fukuda¹, H. Asai¹, J. Hattori¹, T. Mori¹, Y. Morita¹, W. Mizubayashi¹, M. Masahara¹, S. Migita¹, H. Ota¹, K. Endo¹, T. Matsukawa¹ (1.AIST (Japan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-06] Enhancement of Capacitance Benefit by Drain Offset Structure in TFET Circuit Speed Associated with Tunneling Probability Increase

^○H. Asai¹, T. Mori¹, T. Matsukawa¹, J. Hattori¹, K. Endo¹, K. Fukuda¹ (1.AIST (Japan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-07] Benchmarking the Impact of Work Function Variations on Cell Stability of Low-Voltage 6T SRAMs with Non-planar and Planar TMDFETs

^○C. -T. Zheng¹, P. Su¹, C. -T. Chuang¹ (1.National Chiao Tung Univ. (Taiwan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-08] Improved Hetero-Gate-Dielectric Tunnel Field-Effect Transistors

W. Y. Choi¹,^○J. W. Lee¹ (1.Sogang Univ. (Korea))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-09] Numerical Design for Power Integrity Analysis of Tunnel Field Effect Transistors

^○C. Tanaka¹, T. Tanamoto¹, M. Koyama¹ (1.Toshiba Corp. (Japan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-10] Effects of Si Recess Structure on Performance and Reliability in High Voltage n-MOSFETs

C. -Y. Chen¹, J. F. Chen¹,^○Y. -L. Tsai¹, H. -T. Hsu², H. -P. Hwang² (1.National Cheng Kung Univ. (Taiwan), 2.Powerchip Tech. Corp. (Taiwan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-11] Theoretical Investigation of the Performance Improvement in GeSn/SiGeSn hetero Line Tunneling FET (HL-TFET)

^○H. Wang¹, G. Han¹, Y. Liu¹, C. Zhang¹, J. Zhang¹, Y. Hao¹ (1.Xidian Univ. (China))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-12] Ge-cap Quantum Well Bulk FinFET for 5nm node CMOS Integration

^○E. D. Kurniawan^1,2, S. -Y. Yang¹, Y. -Y. Yang¹, K. -H. Peng¹, V. Thirunavukkarasu^1,2, Y. -H. Lin³, Y. -C. Wu¹ (1.National Tsing Hua Univ. (Taiwan), 2.Academia Sinica (Taiwan), 3.National United Univ. (Taiwan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-13 (Late News)] Hot-carrier Induced Drastic Off-state Leakage Current Degradation in STI-based N-channel LDMOS

^○K. Takahashi¹, K. Komatsu¹, T. Sakamoto¹, K. Kimura¹, F. Matsuoka¹ (1.Toshiba Electronic Devices & Storage Corp. (Japan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-14 (Late News)] TCAD simulation of planar single-gate Si tunnel FET with average subthreshold swing less than 60 mV/dec for 0.3 V operation

^○K. Kukita¹, T. Uechi¹, J. Shimokawa¹, M. Goto¹, Y. Yokota¹, S. Kawanaka¹, T. Tanamoto², M. Koyama², H. Tanimoto¹, S. Takagi³ (1.Toshiba Memory Corp. (Japan), 2.Toshiba Corp. (Japan), 3.Univ. of Tokyo (Japan))

2017 International Conference on Solid State Devices and Materials |PDF ダウンロード

763件中(571 - 580)