[B-6-02] Integration of Low-k Low Temperature 400°C SiCO as Offset Spacer in view of 3D Sequential Integration

^○C. Fenouillet-Beranger¹, L. Brunet¹, E. Arnoux¹, V. Lu¹, V. Beugin¹, C. Guerin¹, S. Del Medico², V. Loup¹, M.-P. Samson², B. Previtali¹, C. Tabone¹, N. Rambal¹, N. Rochat¹, D. Benoit², F. Allain¹, G. Romano¹, T. Artemisia¹, M. Casse¹, X. Garros¹, H. Dansas¹, A. Grenier¹, P. Batude¹, M. Vinet¹ (1.Inst. CEA/LETI (France), 2.Indus. STMicroelectronics (France))

2018 International Conference on Solid State Devices and Materials |2018年9月12日(水) 15:45 〜 16:00 |PDF ダウンロード

[B-6-03] Low-Resistive, Highly-Reflowable Aluminum Contact Plug with Co Wetting Film

^○K. Omori¹, M. Inoue¹, T. Maruyama¹, M. Matsuura¹ (1.Renesas Electronics Corp. (Japan))

2018 International Conference on Solid State Devices and Materials |2018年9月12日(水) 16:00 〜 16:15 |PDF ダウンロード

[B-6-04] RTA-Temperature Dependence of Electrical Characteristics of PVD-TiN Metal Gate SOI-MOSFETs Fabricated on Half-Inch Minimal Wafers

^○Y. Liu¹ (1.AIST (Japan))

2018 International Conference on Solid State Devices and Materials |2018年9月12日(水) 16:15 〜 16:30 |PDF ダウンロード

[B-7-01 (Invited)] Progress of Single-Gate Vertical Channel (SGVC) 3D NAND Technology and Introduction of 3D AND-type NVM

^○H.-T. Lue¹ (1.Macronix Int’l. Co., Ltd. (Taiwan))

2018 International Conference on Solid State Devices and Materials |2018年9月13日(木) 09:00 〜 09:30 |PDF ダウンロード

[B-7-02] Effect of String Tapering on Threshold Voltage Distribution and Its Mitigation in a Vertical Channel 3D NAND Flash Memory

U.M. Bhatt¹, A. Kumar², M. Pakala²,^○ S.K. Manhas¹ (1.Indian Inst. of Tech. (IIT), Roorkee (India), 2.Applied Materials Inc. (USA))

2018 International Conference on Solid State Devices and Materials |2018年9月13日(木) 09:30 〜 09:45 |PDF ダウンロード

[B-7-03] Hot Carrier Programing Performance Study on 2T 40nm Flash Memory Cell Array For Variability Evaluation

^○T. Kempf^1,2,3, V. Della Marca², M. Mantelli¹, J. Postel-Pellerin², J.-M. Portal², P. Masson³, A. Regnier¹, S. Niel¹ (1.STMicroelectronics (France), 2.IM2NP Lab., Univ. of Aix-Marseille (France), 3.Polytech'Lab, Univ. of Nice Sophia-Antipolis (France))

2018 International Conference on Solid State Devices and Materials |2018年9月13日(木) 09:45 〜 10:00 |PDF ダウンロード

[B-7-04] Influence of Material Parameters on the Performance of Accumulation Mode DRAM

^○M.R. Ansari¹, N. Navlakha¹, J.T. Lin², A. Kranti¹ (1.Indian Institute of Technology Indore (India), 2.National Sun Yat-Sen University (Taiwan))

2018 International Conference on Solid State Devices and Materials |2018年9月13日(木) 10:00 〜 10:15 |PDF ダウンロード

[B-7-05] Vertical Double-Gate 1T DRAM with an Asymmetric Oxide Barrier for Significant Enhancement of Data Retention

^○J.Y. Lee¹, J. Ha², I.H. Cho², S. Cho¹ (1.Gachon University (Korea), 2.Myongji University (Korea))

2018 International Conference on Solid State Devices and Materials |2018年9月13日(木) 10:15 〜 10:30 |PDF ダウンロード

[B-7-06 (Late News)] First Implementation of MONOS Flash Memory in SOTB-CMOS

^○K. Maekawa¹, H. Makiyama¹, Y. Yamamoto¹, Y. Omizu¹, H. Yamakoshi¹, K. Sonoda¹, H. Yanagita¹, H. Shinkawata¹, T. Hashimoto¹, Yasuo Yamaguchi¹, Tomohiro Yamashita¹ (1.Renesas Electronics Corp. (Japan))

2018 International Conference on Solid State Devices and Materials |2018年9月13日(木) 10:30 〜 10:45 |PDF ダウンロード

[C-1-01 (Invited)] Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires: Recent Progress in CMOS Integration and in Advanced Inline Metrology

^○H. Mertens¹, R. Ritzenthaler¹, D. Mocuta¹, N. Horiguchi¹ (1.IMEC (Belgium))

2018 International Conference on Solid State Devices and Materials |2018年9月11日(火) 14:00 〜 14:30 |PDF ダウンロード