2015 International Conference on Solid State Devices and Materials

2015年9月27日〜 2015年9月30日
Sapporo Convention Center, Sapporo, Japan

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[PS-3-7] 1/f Noise Performances and Noise Sources of Accumulation Mode Si(100) n-MOSFETs

^○P. Gaubert¹, A. Teramoto¹, S. Sugawa¹ (1.Tohoku Univ.(Japan))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-8] ON Current Enhancement of Nanowire Schottky Barrier Tunnel FET

^○K. Takei¹, S. Hashimoto¹, J. Sun¹, X. Zhang¹, S. Asada¹, T. Xu¹, T. Wakamizu¹, T. Matsukawa², M. Masahara², T. Watanabe¹ (1.Waseda Univ., 2.AIST(Japan))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-9] Novel 5-State Latch Using Double-Peak Negative Differential Resistance (NDR) and Standard Ternary Inverter (STI)

^○S. Shin¹, K. R. Kim¹ (1.UNIST(Korea))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-10] Impacts of Threshold Voltage Design for Monolithic 3D 6T SRAM with Si and InGaAs-n/Ge-p Devices considering Interlayer Coupling

^○K. C. Yu¹, C. H. Yu¹, V. P. H. Hu¹, P. Su¹, C. T. Chuang¹ (1.National Chiao Tung Univ.(Taiwan))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-11] Multi-Threshold Voltages in Ultra-thin-body Devices by Asymmetric Dual-Gate Structure

^○H. Kim¹, J. Park¹, M. W. Kwon¹, S. Hwang¹, B. G. Park¹ (1.Seoul National Univ.(Korea))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-12] Investigation of Trap Properties in High-k/Metal Gate pMOSFETs of Higher Al Energy and Concentration Ion Implantation on Random Telegraph Noise

^○T. H. Kao¹, S. J. Chang¹, Y. K. Fang¹, P. C. Huang¹, Y. K. Su¹, Y. J. Shen¹, C. Y. Wu², S. L. Wu² (1.National Cheng Kung Univ., 2.Cheng Shiu Univ.(Taiwan))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-13] The Limits of Applicability of the Analytic Model for Hot Carrier Degradation

^○M. Jech¹, P. Sharma¹, S. Tyaginov^1,2, F. Rudolf¹, T. Grasser¹ (1.Tech. Univ. of Vienna, 2.Ioffe Physical-Techn. Inst.(Austria))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-14] Investigation of Backgating Effect on Superlinear Onset of Output Characteristics for UTB III-V Heterojunction Tunnel FET

^○S. E. Huang¹, M. L. Fan¹, P. Su¹ (1.National Chiao Tung Univ.(Taiwan))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-15] Optimized Nanowire Diameter for III-V Homojunction and Heterojunction Gate-All-Around Tunnel FETs

^○Y. W. Wang¹, P. Su¹ (1.National Chiao Tung Univ.(Taiwan))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

[PS-3-16] Transmission Line Model and Transconductance Method for Layout Dependent Source Resistance Extraction in Multi-Finger MOSFETs

^○Y. Z. Lo¹, J. C. Guo¹ (1.National Chiao Tung Univ.(Taiwan))

2015 International Conference on Solid State Devices and Materials |PDF ダウンロード

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