[A-8-2] A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond

M. Ishibashi, K. Horita, M. Sawada, M. Kitazawa, M. Igarashi, T. Kuroi, T. Eimori, K. Kobayashi, M. Inuishi, Y. Ohji (1.Process Technology Development Div, Renesas Technology Corp.)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-8-3] Theoretical Investigation of Electrical Performance and Band Structure of P-MOSFETs with Si1-xGex Source/Drain Stressors

Kah-Wee Ang, Yong-Tian Hou, Jagar Singh, Ming-Fu Li, Yee-Chia Yeo (1.Department of Electrical and Computer Engineering, National University of Singapore, 2.Institute of Microelectronics)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-8-4] In-Plane Anisotropy of MOS Inversion Layer Mobility on Silicon (100), (110) and (111) surfaces

H. Irie, K. Kita, K. Kyuno, A. Toriumi (1.Department of Materials Science, School of Engineering, The University of Tokyo)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-9-1] Nanoscale Device Simulation at the Scaling Limit and Beyond

Anisur Rahman, Gerhard Klimeck, Nizami Vagidov, Timothy B. Boykin, Mark Lundstrom (1.School of ECE, Network for Computational Nanotechnology Purdue University, 2.Department of EE, State University of New York, 3.Department of Elec. and Comp. Engineering, University of Alabama)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-9-2] Nanoscale Quasi-Ballistic MOSFETs in Reflection-Transmission Model

Kenji Natori, Takashi Kurusu (1.Institute of Applied Physics, University of Tsukuba)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-9-3] Quantitative Understanding of Mobility Degradation in High Effective Electric Field Region in MOSFETs with Ultra-thin Gate Oxides

Takamitsu Ishihara, Junji Koga, Shin-ichi Takagi (1.Advanced LSI Technology Laboratory, Research and Development Center, Toshiba Corporation, 2.Department of Frontier Informatics, Graduate School of Frontier Science, The University of Tokyo)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-9-4] Determination of tunnel mass and thickness of gate oxide including poly-Si/SiO Si/SiO2 interfacial transition layers

Hiroshi Watanabe, Daisuke Matsushita, Kouichi Muraoka (1.Advanced LSI Technology Laboratory)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-10-1] Halo and LDD Engineering for Multiple VT High Performance Analog Devices in 0.13μm CMOS Technology

J. C. Guo, W.Y. Lien, C. C. Liur, C.M. Wu (1.Department of Electronics Engineering, National Chiao Tung University, 2.Research Development Center, Taiwan Semiconductor Manufacturing Corp.)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-10-2] A Large-Signal MOSFET Model Based on Transient Carrier Response for RF Circuits

Kazufumi Watanabe, Koji Kotani, Akinobu Teramoto, Shigetoshi Sugawa, Tadahiro Ohmi (1.Graduate School of Engineering, Tohoku University, 2.New Industry Creation Hatchery Center, Tohoku University)

2004 International Conference on Solid State Devices and Materials |PDF Download

[A-10-3] A Quantum Mechanical Corrected SPICE Model for Ultrathin Oxide MOSFETs’ Gate Tunneling Current Simulation

Yiming Li, Shao-Ming Yu, Jam-Wem Lee (1.Department of Computational Nanoelectronics, National Nano Device Laboratories, 2.Microelectronics and Information Systems Research Center, National Chiao Tung University, 3.Department of Computer and Information Science, National Chiao Tung University)

2004 International Conference on Solid State Devices and Materials |PDF Download

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