Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[18p-G203-1~18] 13.5 Semiconductor devices and related technologies

Sun. Mar 18, 2018 1:15 PM - 6:00 PM G203 (63-203)

Masumi Saitoh(TOSHIBA), Kousuke Miyaji(Shinshu Univ.)

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1:15 PM - 1:30 PM

[18p-G203-1] Lowering data retention voltage in static random access memory array by post-fabrication self-improvement of cell stability by multiple stress application

〇Tomoko Mizutani¹, Kiyoshi Takeuchi¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (1.IIS, Univ. of Tokyo)

1:30 PM - 1:45 PM

[18p-G203-2] Soft Errors in Thin-BOX SOI SRAMs Exposed to Heavy Ion Radiation

〇Daisuke Kobayashi¹, Kazuyuki Hirose¹, Taichi Ito², Yuya Kakehashi², Osamu Kawasaki², Takahiro Makino³, Takeshi Ohshima³, Daisuke Matsuura⁴, Takanori Narita⁴, Masahiro Kato⁴, Shigeru Ishii⁴, Kazunori Masukawa⁴ (1.ISAS/JAXA, 2.R&D/JAXA, 3.QST, 4.MHI Ltd.)

1:45 PM - 2:00 PM

[18p-G203-3] Energy performance of nonvolatile SRAM using hierarchical store-free shutdown architecture

〇(D)Daiki Kitagata¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

2:00 PM - 2:15 PM

[18p-G203-4] Electrical characteristics of MOSFETs using anti-ferroelectric thin films as gate insulators

〇Masashi Yamaguchi¹, Takahiro Gotow¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.The Univ. of Tokyo, Faculty of Eng.)

2:15 PM - 2:30 PM

[18p-G203-5] Electrical characteristics of La₂O₃/Si MOSFETs with ferroelectric-type hysteresis

〇Kiyoshi Endo¹, Kimihiko Kato¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Tokyo Univ.)

2:30 PM - 2:45 PM

[18p-G203-6] Necessity of Transient Analysis in Simulation of Ferroelectric Negative Capacitance Devices

〇Hiroyuki Ota¹, Shinji Migita¹, Tsutomu Ikegami¹, Junichi Hattori¹, Hidehiro Asai¹, Koichi Fukuda¹, Akira Toriumi² (1.AIST, 2.Univ. of Tokyo)

2:45 PM - 3:00 PM

[18p-G203-7] Design of a new piezoelectronic transistor and its device and circuit performances

〇Yusaku Shiotsu¹, Shuu'ichiro Yamamoto¹, Yusuke Shuto², Hiroshi Hunakubo³, Minoru Kurosawa⁴, Satoshi Sugahara¹ (1.FIRST., Tokyo Inst. of Tech., 2.ISEL., Tokyo Inst. of Tech., 3.Dept. of Mater. Sci. and Eng., Tokyo Inst. of Tech., 4.Dept. of Electr. and Electron. Eng., Tokyo Inst. of Tech.)

3:00 PM - 3:15 PM

[18p-G203-8] Piezoelectronic magnetoresistive-device and its low-voltage MRAM application

〇Yota Takamura¹, Shu'ichiro Yamamoto², Hiroshi Funakubo³, Minoru K. Kurosawa¹, Shigeki Nakagawa¹, Satoshi Sugahara² (1.Dept. of Electr. and Electron. Eng., Tokyo Inst. of Tech., 2.Lab. for Future Interdisciplinary Research of Sci. and Tech. (FIRST), Tokyo Inst. of Tech., 3.Dept. of Mater. Sci. and Eng., Tokyo Inst. of Tech.)

3:15 PM - 3:30 PM

[18p-G203-9] Pure CMOS Few-Time Programmable Memories using a Combination of Gate-Ox Anti-fuse and Poly-Si Fuse

〇Mari Matsumoto¹, Masato Oda¹, Shinichi Yasuda¹ (1.Toshiba R&D Center)

3:45 PM - 4:00 PM

△ [18p-G203-10] Evaluation of multilevel memory characteristics of Ta₂O_5-δ ReRAM with controlled oxygen vacancy

〇(M2C)Yuanlin Li¹, Reon Katsumura¹, Mika Gronroos¹, Atsushi Tsurumaki-Fukuchi¹, Masashi Arita¹, Yasuo Takahashi¹, Hideyuki Andoh², Takashi Morie² (1.Hokkaido Univ., 2.Kyushu Inst. Tech.)

4:00 PM - 4:15 PM

△ [18p-G203-11] In-situ TEM Observation of Operational Instability of CBRAM

〇Satoshi Muto¹, Shinya Sakai¹, Atsushi Tsurumaki-Fukuchi¹, Masashi Arita¹, Yasuo Takahashi¹ (1.Hokkaido Univ.)

4:15 PM - 4:30 PM

[18p-G203-12] Spike-Induced Metal-Insulator Transition in VO₂ Neuron Circuits

〇Takeaki Yajima¹, Tomonori Nishimura¹, Akira Toriumi¹ (1.The Univ. of Tokyo)

4:30 PM - 4:45 PM

▼ [18p-G203-13] Impact of solid-state memristor variability on perceptron supervised learning via STDP

〇Radu M Berdan¹, Takao Marukame¹, Yoshifumi Nishi¹ (1.Toshiba RDC)

4:45 PM - 5:00 PM

[18p-G203-14] Evaluation of ReRAM Considering Program-Verify Cycles and ECC Strength

〇Yutaka Adachi¹, Ken Takeuchi¹ (1.Chuo Univ.)

5:00 PM - 5:15 PM

[18p-G203-15] Burst Error Reduction for Improvement of LDPC Correction Capability in TLC NAND Flash Memories

〇Toshiki Nakamura¹, Yoshiaki Deguchi¹, Ken Takeuchi¹ (1.Chuo Univ.)

5:15 PM - 5:30 PM

[18p-G203-16] 3D-TLC NAND Flash memory-based Value-Aware SSD for Image Recognition System with Deep Neural Network

〇Yoshiaki Deguchi¹, Toshiki Nakamura¹, Ken Takeuchi¹ (1.Chuo Univ.)

5:30 PM - 5:45 PM

[18p-G203-17] Data Compression Technique for Reliability Enhancement of TLC NAND Flash Memory

〇Yoshiaki Deguchi¹, Hikaru Watanabe¹, Ken Takeuchi¹ (1.Chuo Univ.)

5:45 PM - 6:00 PM

[18p-G203-18] V_TH Modulation with Word-Line Unit of TLC NAND Flash Memories Considering Write Frequencies of Data

〇Yoshiaki Deguchi¹, Ken Takeuchi¹ (1.Chuo Univ.)

Session information

[18p-G203-1~18] 13.5 Semiconductor devices and related technologies

[18p-G203-1] Lowering data retention voltage in static random access memory array by post-fabrication self-improvement of cell stability by multiple stress application

[18p-G203-2] Soft Errors in Thin-BOX SOI SRAMs Exposed to Heavy Ion Radiation

[18p-G203-3] Energy performance of nonvolatile SRAM using hierarchical store-free shutdown architecture

[18p-G203-4] Electrical characteristics of MOSFETs using anti-ferroelectric thin films as gate insulators

[18p-G203-5] Electrical characteristics of La₂O₃/Si MOSFETs with ferroelectric-type hysteresis

[18p-G203-6] Necessity of Transient Analysis in Simulation of Ferroelectric Negative Capacitance Devices

[18p-G203-7] Design of a new piezoelectronic transistor and its device and circuit performances

[18p-G203-8] Piezoelectronic magnetoresistive-device and its low-voltage MRAM application

[18p-G203-9] Pure CMOS Few-Time Programmable Memories using a Combination of Gate-Ox Anti-fuse and Poly-Si Fuse

△ [18p-G203-10] Evaluation of multilevel memory characteristics of Ta₂O_5-δ ReRAM with controlled oxygen vacancy

△ [18p-G203-11] In-situ TEM Observation of Operational Instability of CBRAM

[18p-G203-12] Spike-Induced Metal-Insulator Transition in VO₂ Neuron Circuits

▼ [18p-G203-13] Impact of solid-state memristor variability on perceptron supervised learning via STDP

[18p-G203-14] Evaluation of ReRAM Considering Program-Verify Cycles and ECC Strength

[18p-G203-15] Burst Error Reduction for Improvement of LDPC Correction Capability in TLC NAND Flash Memories

[18p-G203-16] 3D-TLC NAND Flash memory-based Value-Aware SSD for Image Recognition System with Deep Neural Network

[18p-G203-17] Data Compression Technique for Reliability Enhancement of TLC NAND Flash Memory

[18p-G203-18] V_TH Modulation with Word-Line Unit of TLC NAND Flash Memories Considering Write Frequencies of Data

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Session information

[18p-G203-1~18] 13.5 Semiconductor devices and related technologies

△ [18p-G203-10] Evaluation of multilevel memory characteristics of Ta2O5-δ ReRAM with controlled oxygen vacancy

△ [18p-G203-11] In-situ TEM Observation of Operational Instability of CBRAM

▼ [18p-G203-13] Impact of solid-state memristor variability on perceptron supervised learning via STDP

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△ [18p-G203-10] Evaluation of multilevel memory characteristics of Ta₂O_5-δ ReRAM with controlled oxygen vacancy