[E-8-3] A Low Power Multiplier Using Adiabatic Charging Binary Decision Diagram Circuit

Shunji Nakata、Takakuni Douseki、Yuichi Kado (1.NTT Telecommunications Energy Laboratories)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[E-9-1] Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs

Hiroshi Koura、Makoto Takamiya、Toshiro Hiramoto (1.Institute of Industrial Science, University of Tokyo、2.VLSI Design and Education Center, University of Tokyo)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[E-9-2] A Split Level BUS for Low Power High Speed LSI's

Shoichiro Kawashima、Makoto Hamaminato、Isao Fukushi (1.LSI technology Lab. FUJITSU Laboratories Ltd.)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[E-9-3] An Effective Routing Methodology for High-Speed DRAM in the Era Beyond 0.2 μm Technology

Jae-Kyung Wee、Jung-Won Suh、Joo-Sun Choi (1.Memory Product & Technology Development Division, Hyundai Electronics)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード

[LE-2-1] High Performance Sub-0.1 μm Dynamic Threshold MOSFET Using Indium Channel Implantation

S. J. Chang、C. Chen、Y. J. Lee、S. D. Wu、C. Y. Chang、T. S. Chao、J. W. Chou、Tony. Lin、T. P. Chen、S. W. Sun (1.Department of Electronic Engineering, National Chiao Tung University、2.National Nano Device Labs.、3.United Microelectronics Corp., Technology Development Division)

1999 International Conference on Solid State Devices and Materials |PDF ダウンロード