[E-2-02] Effect of SiGe Layer Thickness in Starting Substrate on Electrical Properties of Ultrathin Body Ge-on-Insulator pMOSFET Fabricated by Ge Condensation

^○K. -W. Jo¹, W. -K. Kim¹, M. Takenaka¹, S. Takagi¹ (1.Univ. of Tokyo (Japan))

2017 International Conference on Solid State Devices and Materials |Wed. Sep 20, 2017 4:10 PM - 4:30 PM |PDF Download

[E-2-03] Single and Double Diffusion Breaks in 14nm FinFET and Beyond

^○K. Miyaguchi¹, F. Bufler¹, T. Chiarella¹, P. Matagne¹, N. Horiguchi¹, A. D. Keersgieter¹, G. Eneman¹, A. Spessot¹, B. Parvais^1,2, D. Verkest¹, A. Mocuta¹ (1.IMEC (Belgium), 2.Vrije Universiteit Brussel (Belgium))

2017 International Conference on Solid State Devices and Materials |Wed. Sep 20, 2017 4:30 PM - 4:50 PM |PDF Download

[E-2-04] Insights and Opportunities for Junctionless Gate-All-Around Lateral and Vertical Nanowire FETs

^○A. Veloso¹, P. Matagne¹, E. Simoen¹, A. Chasin¹, B. Kaczer¹, D. Yakimets¹, D. Mocuta¹, N. Collaert¹ (1.IMEC (Belgium))

2017 International Conference on Solid State Devices and Materials |Wed. Sep 20, 2017 4:50 PM - 5:10 PM |PDF Download

[E-2-05] High Performance Top-Gate Zinc Oxide Thin Film Transistor (ZnO TFT) by Combination of Post Oxidation and Annealing

^○K. Kato¹, H. Matsui¹, H. Tabata¹, M. Takenaka¹, S. Takagi¹ (1.Univ. of Tokyo (Japan))

2017 International Conference on Solid State Devices and Materials |Wed. Sep 20, 2017 5:10 PM - 5:30 PM |PDF Download

[E-3-01 (Invited)] Performance Evaluation of III-V Nanowire Broken-Gap TFETs Including Electron-Phonon Scattering Using an Atomistic Mode Space NEGF Technique Enabling Million Atoms NW Simulations.

^○A. Afzalian¹, T. Vasen¹, P. Ramvall¹, D. Lemus², T. Kubis², M. Passlack¹, T. -M. Shen³, J. Wu³ (1.TSMC, Leuven (Belgium), 2.Purdue Univ. (USA), 3.TSMC, Hsinchu (Taiwan))

2017 International Conference on Solid State Devices and Materials |Thu. Sep 21, 2017 9:30 AM - 10:00 AM |PDF Download

[E-3-02] Investigation of TFETs with Vertical Tunneling Path for Low Average Subthreshold Swing

^○S. Glass¹, N. von den Driesch¹, S. Strangio², C. Schulte-Braucks¹, T. Rieger¹, D. Buca¹, S. Mantl¹, Q. -T. Zhao¹ (1.Forschungszentrum Juelich (Germany), 2.Univ. of Udine (Italy))

2017 International Conference on Solid State Devices and Materials |Thu. Sep 21, 2017 10:00 AM - 10:20 AM |PDF Download

[E-3-03] Performance Improvement of Ge-source/Si-channel Hetero-Junction Tunneling FETs: Effects of Annealing Gas and Drain Doping Concentration

^○T. -E. Bae¹, Y. Wakabayashi¹, R. Nakane¹, M. Takenaka¹, S. Takagi¹ (1.Univ. of Tokyo (Japan))

2017 International Conference on Solid State Devices and Materials |Thu. Sep 21, 2017 10:20 AM - 10:40 AM |PDF Download

[E-3-04] Ge p-channel Tunneling FETs with Steep Phosphorus Profile Source Junctions

^○R. Takaguchi¹, R. Matsumura¹, T. Katoh¹, M. Takenaka¹, S. Takagi¹ (1.Univ. of Tokyo (Japan))

2017 International Conference on Solid State Devices and Materials |Thu. Sep 21, 2017 10:40 AM - 11:00 AM |PDF Download

[E-4-01] Design of Steep Slope Negative Capacitance FinFETs for Dense Integration: Matching of Channel and Ferroelectric Capacitances

^○H. Ota¹, J. Hattori¹, H. Asai¹, T. Ikegami¹, K. Fukuda¹, S. Migita¹, A. Toriumi² (1.AIST (Japan), 2.Univ. of Tokyo (Japan))

2017 International Conference on Solid State Devices and Materials |Thu. Sep 21, 2017 2:00 PM - 2:20 PM |PDF Download

[E-4-02] Investigation of Quantum-Induced VT Shift and Backgate-Modulated VT Properties for Ultra-Thin-Body InGaAs-OI/SOI Negative-Capacitance FETs

^○S. -E. Huang¹, C. -L. Yu¹, W. -X. You¹, P. Su¹ (1.National Chiao Tung Univ. (Taiwan))

2017 International Conference on Solid State Devices and Materials |Thu. Sep 21, 2017 2:20 PM - 2:40 PM |PDF Download