136 results (101 - 110)

« Prev
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Next »

[S-II-1] Recent Advance in Multilevel Interconnection

Hiroaki Nakamura (1.NTT LSI Laboratories)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-2] Properties of Direct-Silicided WSi2 Films

A. TANIKAWA, H. OKABAYASHI (1.Microelectronics Res. Labs., NEC Corporation)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-3] Silicided Shallow Junction Formation for Scaled-down CMOS Devices

Kiyonori OHYU, Tadashi SUZUKI, Nobuyoshi NATSUAKI, Yasuo WADA (1.Central Research Laboratory, Hitachi, Ltd.)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-4] Degradation of MOS Characteristics Caused by Internal Stresses in Gate Electrodes

NAOKI YAMAMOTO (1.CENTRAL RESEARCH LABORATORY, HITACHI, LTD.)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-5] Low Resistivity Tungsten/Titanium-Silicide/Silicon Contact for Submicron VLSI

Jyuro Yasui, Shin-ichi Ogawa, Takehito Yoshida, Yasuaki Terui (1.Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd.)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-6] Impurity Effect on Reduction in Thermal Stress of Titanium Silicides

K. Suguro, S. Shima (1.VLSI Research Center, Toshiba Corporation)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-7] Current Status of Developments of Oxide Superconductors

K. Kitazawa, S. Uchida, H. Takagi, K. Kishio, T. Hasegawa, S. Tanaka, K. Fueki (1.University of Tokyo, Faculty of Engineering)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-8] Mo-Silicides Bias-Sputtering and Its Application to Thermally-Stable, Via-Hole-Filled Contact Formation

T. MOGAMI, H. OKABAYASHI, K. KAJIYANA, K. UDA, M. MORIMOTO, H. HOSHINO (1.Microelectronics Res. Labs. and Resources & Environ. Prot. Res. Labs., NEC Corporation)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-9] Low Resistive, High Aspect Ratio Via-Hole Filling System Completely Planarized by Selective W Deposition and Subsequent Etch-Back

K. Shiozaki, K. Mitsuhashi, K. Ohtake, M. Koba (1.Central Research Laboratories, Sharp Corporation)

1987 Conference on Solid State Devices and Materials |PDF Download

[S-II-10] Planarization Mechanism in Flowage Bias Sputter Method

K. Kamoshida, H. Nakamura (1.NTT Electrical Communications Laboratories)

1987 Conference on Solid State Devices and Materials |PDF Download

136 results (101 - 110)

« Prev
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Next »