[B-3-4] High-Performance EEPROMs Using N- and P-Channel Poly-Si TFTs with ECR N20-Plasma Oxide

Nae-In Lee, Jin-Woo Lee, Hyoung-Sub Kim, Chul-Hi Han (1.Department of Electrical Engineering, KAIST, 2.Semiconductor R & D Center, Samsung Electronics Co. Ltd.)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-3-5] Characteristics and Correlated Fluctuations of the Gate and Substrate Current after Oxide Soft-Breakdown

F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam, H. E. Maes (1.IMEC, 2.Department of Information Engineering, The University of Pisa)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-3-6] Experimental Study of the Soft Breakdown I-V Characteristics in Ultrathin SiO2 Layers

Enrique MIRANDA, Jordi SUNE, Rosana RODRIGUEZ, Montserrat NAFRIA, Ferran MARTIN, Xavier AYMERICH (1.Dept. Enginyeria Electronica, Universitat Autonoma de Barcelona)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-4-1] Nanimprint Lithography

S. Y. Chou (1.Princeton Univ.)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-4-2] Surface Preparation, Growth, and Interface Control of Ultrathin Gate Oxides

Yasushiro Nishioka, Kenji Namba, Mieko Matsumura, Tomoyuki Sakoda, Yoshinao Kumagai, Tadahiro Komeda, Hikaru Kobayashi, Tyuji Hoshino, Atsushi Ando, Kazushi Miki (1.Texas Instruments Tsukuba Research and Development Center Limited, 2.The Institute of Scientific & Industrial Researches, Osaka University, 3.Faculty of Pharmaceutical Sciences, Chiba University, 4.Electrotechnical Laboratory (ETL))

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-4-3] Formation of Silicon Oxynitride Films with High Nitrogen Concentration at Low Temperatures

Toshiko Mizokuro, Kenji Yoneda, Yoshihiro Todokoro, Hikaru Kobayashi (1.Institute of Scientific and Industrial Research, Osaka University, 2.ULSI Process Technology Development Center, Matsushita Electronic Corporation, 3.Research Planning Department, Corporate Research Division, Matsushita Electric Industrial Co., Ltd., 4.PRESTO, Japan Science and Technology Corporation)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-4-4] Plasma Damage Free Gate Process Using CMP for 0.1um MOSFETs

Tomohiro Saito, Atsushi Yagishita, Seiji Inumiya, Kazuaki Nakajima, Yasushi Akasaka, Yoshio Ozawa, Hiroyuki Yano, Katsuhiko Hieda, Kyoichi Suguro, Tsunetoshi Arikado, Katsuya Okumura (1.Microelectronics Engineering Laboratory, Toshiba Corporation)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-4-5] Through-the-Gate Implanted (TGI) CMOS Technology with Advanced Shallow Trench Isolation

U. Schwalke, M. Fuldner, W. Zatsch, K. Bothe, D. Hadawi, I. Janssen, P. Schon (1.Siemens Corporate Technology, Siemens Semiconductor Division)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-5-1] Scalning to a 1.0V-1.5V, sub 0.1um Gate Length CMOS Technology: Perspective and Challanges

M. Rodder, I.-C. Chen, S. Hattangady, J. C. Hu (1.Silicon Technology Development, Texas Instruments, 2.WSMC)

1998 International Conference on Solid State Devices and Materials |PDF Download

[B-5-2] Ultra-Low Energy Ion Implantation for 0.1 Micron CMOS Devices

David Armour (1.Applied Materials Implant Division)

1998 International Conference on Solid State Devices and Materials |PDF Download