[P-5-2] Low-Power Image-Segmentation VLSI Design based on a Pixel-Block Scanning Architecture
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
587件中(481 - 490)
[P-5-3] A Digital-Pixel-Sensor-Based Global Feature Extraction VLSI for Real-Time Image Recognition
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-4] Analytic Parameter Extraction of On-chip Spiral Inductors using a Modified Skin Effect Model
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-5] An Optimal Design Method for Even-Stage Ring Oscillators with a CMOS Latch
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-6] Additional 12% Power Reduction in Practical Digital Chips of Low-Power Design using Post-Fabrication Clock-Timing Adjustment
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-7] Battery-less Telemetry System with a Closed-loop Power Control for Bio-Implantable Applications
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-8] Low Gate Charge Power VDMOSFETs with Dual-Gate Floating NP Well Design
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-9] A Novel Match-line Charging Control Scheme with a New Sense Amplifier for High-Speed and Low-Power Content-Addressable Memory
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-10] A Novel Inductance Evaluation Method for Clip-Type Inductors and Meander Inductors Under the Impedance Matched Condition
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード
[P-5-11L] A 33% Improvement in Efficiency of Wireless Inter-Chip Power Delivery by Thin Film Magnetic Material
2008 International Conference on Solid State Devices and Materials |PDF ダウンロード