[D-6-3] Extremely Small Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire MOSFETs

K. Mao¹, T. Mizutani¹, A. Kumar¹, T. Saraya¹, T. Hiramoto¹ (1.Univ. of Tokyo , Japan)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-6-4] Enhanced Performance of Tri-Gate Transistors with Gnox Using Optimized Novel SOI Realization Technology

S. H. Kim^1,2, H. J. Bae¹, C. W. Oh¹, D. W. Kim¹, S. Yamada¹, G. Y. Jin¹, Y. Roh² (1.Samsung Electronics, 2.Sungkyunkwan Univ. , Korea)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-7-1] Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications

K. Cheng¹, A. Khakifirooz¹, P. Kulkarni¹, S. Ponoth¹, B. Haran¹, A. Kumar¹, T. Adam¹, A. Reznicek¹, N. Loubet², H. He¹, J. Kuss¹, M. Wang¹, T. M. Levin¹, F. Monsieur², Q. Liu², R. Sreenivasan¹, J. Cai¹, A. Kimball¹, S. Mehta¹, S. Luning³, Y. Zhu¹, Z. Zhu¹, T. Yamamoto⁴, A. Bryant¹, C. H. Lin¹, S. Naczas¹, H. Jagannathan¹, L. F. Edge¹, S. Allegret-Maret², A. Dube¹, S. Kanakasabapathy¹, S. Schmitz¹, A. Inada⁴, S. Seo¹, M. Raymond³, Z. Zhang¹, A. Yagishita⁵, J. Demarest¹, J. Li¹, M. Hopstaken¹, N. Berliner¹, A. Upham¹, R. Johnson¹, S. Holmes¹, T. Standaert¹, M. Smalley¹, N. Zamdmer¹, Z. Ren¹, T. Nagumo⁴, T. Wu, H. Bu, V. Paruchuri, D. Sadana, V. Narayanan, W. Haensch, J. O'Neill, T. Hook, M. Khare, G. Shahidi, B. Doris¹ (1.IBM, 2.STMicroelectronics, 3.GLOBALFOUNDRIES, 4.Renesas, 5.Toshiba , USA)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-7-2] Carrier Transport Mechanisms in Schottky Barrier Source/Drain Nanowire FETs with Lateral Silicidation Process

T. Ishikawa¹, M. Saitoh¹, K. Ota¹, C. Tanaka¹, T. Numata¹ (1.Toshiba Corp. , Japan)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-7-3] Advantages of Silicon Nanowire MOSFETs over Planar Ones Investigated from the Viewpoints of Static and Noise Properties

W. Feng^1,2, R. Hettiarachchi^1,2, S. Sato³, K. Kakushima³, M. Niwa^1,2, H. Iwai³, K. Yamada^1,2, K. Ohmori^1,2 (1.Univ. of Tsukuba, 2.CREST-JST, 3.Tokyo Tech , Japan)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-8-1] A Consistent Modeling Framework to Explain Negative Bias Temperature Instability (NBTI) DC Stress, Recovery and AC Experiments

S. Mahapatra¹, A. E. Islam², S. Deora¹, V. D. Maheta¹, M. A. Alam² (1.IIT Bombay , India, 2.Purdue Univ. , USA)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-8-2] HCI and NBTI Induced statistical Variability in CMOS Transistors

A. Cathignol¹, F. Cacho², X. Federspiel², D. Roy² (1.IBM, 2.STMicroelectronics , France)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-8-3] Compact Reaction-Diffusion Model for Accurate NBTI Prediction

C. Ma^1,3, M. Miyake¹, H. J. Mattausch¹, K. Matsuzawa², T. Iizuka², T. Hozhida², A. Kinoshita², T. Arakawa², J. He³, M. Miura-Mattausch¹ (1.Hiroshima Univ., 2.STARC , Japan, 3.Peking Univ. , China)

2011 International Conference on Solid State Devices and Materials |PDF Download

[D-8-4] Enhanced Degradation by NBT stress in Si Nanowire Transistor

K. Ota¹, M. Saitoh¹, C. Tanaka¹, Y. Nakabayashi¹, K. Uchida², T. Numata¹ (1.Toshiba Corp., 2.Tokyo Tech , Japan)

2011 International Conference on Solid State Devices and Materials |PDF Download

[E-1-1] Investigation of the Electrical Properties of Ge/High-k Gate Stack: GeO₂ VS Si-cap

J. Mitard¹, F. Bellenger¹, L. Witters¹, B. De Jaeger¹, B. Vincent¹, L. Nyns¹, K. Martens¹, E. Vrancken¹, G. Wang¹, D. Lin¹, R. Loo¹, M. Caymax¹, K. De Meyer¹, M. Heyns¹, N. Horiguchi¹ (1.IMEC , Belgium)

2011 International Conference on Solid State Devices and Materials |PDF Download