[PS-1-21 (Late News)] Circuit speed oriented device design scheme for double gate hetero tunnel FETs

K. Fukuda^1,2, N. Nogami², S. Kunisada²,^○Y. Miyamoto² (1.AIST (Japan), 2.Tokyo Tech (Japan))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 11:25 〜 11:27 |PDF ダウンロード

[PS-1-22 (Late News)] Comparison of Voronoi and Cuboid Methods for Work Function Fluctuation and Suppression by Using Stacked-metal Gate on Gate-All-Around Nanowire n-MOSFETs

^○Y.-S. Yang¹, W.-L. Sung¹, M.-H. Chuang¹, Y. Li¹ (1.National Chiao Tung Univ. (Taiwan))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 11:27 〜 11:29 |PDF ダウンロード

[PS-1-23 (Late News)] Improved Electro-Thermal Performance in FinFETs using SOD Technology for 7nm node High Performance Logic Devices

^○V. Sankatali¹, A. Sudarsanan¹, K. Nayak¹ (1.Indian Inst. of Tech. Hyderabad (India))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 11:29 〜 11:31 |PDF ダウンロード

[PS-1-24 (Late News)] High Performance Negative Capacitance Field-Effect Transistor Featuring Low Off-State Current, High On/Off Current Ratio, and Steep Sub-60 mV/dec Swing

^○C. Liu¹, H.-H. Chen¹, Y.-C. Tung¹, W.-C. Wang¹, B.-Y. Shih¹, S.-Y. Hsiung¹, S.-A. Wang², Y.-C. Fan³, T.-M. Lee³, C.-L. Lin³, W.-C. Chou¹, C.-H. Cheng², H.-H. Hsu³ (1.National Chiao Tung Univ. (Taiwan), 2.National Taiwan Normal Univ. (Taiwan), 3.National Taipei Univ. of Tech. (Taiwan))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 11:31 〜 11:33 |PDF ダウンロード

[PS-2-01] Spike Timing Dependent Plasticity Characteristics of Tunnel FET based MONOS Memory for Low Power Neural Network Circuits

^○H. Kino¹, T. Fukushima¹, T. Tanaka¹ (1.Tohoku Univ. (Japan))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 10:45 〜 10:47 |PDF ダウンロード

[PS-2-02] Investigation of Adaptive Weight Quantization in Application for Convolutional Neuromorphic System Using Gated Schottky Diode

^○D. Kwon¹, S. Lim¹, J.-H. Bae¹, S.-T. Lee¹, H. Kim¹, Y.-T. Seo¹, G. Yeom¹, B.-G. Park¹, J.-H. Lee¹ (1.Seoul National Univ. (Korea))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 10:47 〜 10:49 |PDF ダウンロード

[PS-2-03] Synapse Device for Low Voltage Operation and High Conductance Linearity Using Positive Feedback Field Effect Transistor

^○S. Kim^1,2, M.-W. Kwon¹, K. Park¹, M.-H. Baek¹, S. Hwang¹, T. Jang¹, J. Lee¹, B.-G. Park¹ (1.Seoul National Univ. (Korea), 2.Samsung Electronics Ltd. (Korea))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 10:49 〜 10:51 |PDF ダウンロード

[PS-2-04] Weight Update / Inhibition Method for NOR Flash Based Polysilicon Synapse Array

^○M.-H. Baek¹, T. Jang¹, S. Hwang¹, S. Kim¹, B.-G. Park¹ (1.Seoul National Univ. (Korea))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 10:51 〜 10:53 |PDF ダウンロード

[PS-2-05] Impact of Low Temperature Formed GeO_x/Al₂O₃ Tunneling Layer on Reliability of Junctionless Poly-Ge Charge-Trapping Flash Memory Device

^○T.-Y. Chiang¹, K.-S. Chang-Liao¹, H.-K. Fang¹, P.-Y. Lin¹, W.-H. Huang², C.-H. Shen², J.-M. Shieh² (1.National Tsing Hua Univ. (Taiwan), 2.Taiwan Semiconductor Research Institute (Taiwan))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 10:53 〜 10:55 |PDF ダウンロード

[PS-2-06] Optimal Bias Condition of Dummy WL for Sub-Block Erase Operation in 3D NAND Flash Memory

^○Y. Jeong¹, I. Ham¹, M. Kang¹ (1.Korea National Univ. of Transportation (Korea))

2019 International Conference on Solid State Devices and Materials |2019年9月4日(水) 10:55 〜 10:57 |PDF ダウンロード