[M-6-2] Spin-transistor characteristics of pseudo-spin-MOSFETs monolithically-integrated by utilizing a multi-project-wafer CMOS chip

R. Nakane^1,5, Y. Shuto^2,3,5, H. Sukegawa^4,5, Z.C. Wen^4,5, S. Yamamoto^2,5, S. Mitani^4,5, M. Tanaka^1,5, K. Inomata^4,5, S. Sugahara^2,5 (1.Univ. of Tokyo, 2.Tokyo Institute of Technology, 3.Kanagawa Academy of Science and Technology, 4.National Institute for Materials Science, 5.CREST, Japan Science and Technology Agency (Japan))

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[M-6-3] A 4x4 Nonvolatile Multiplier Using Novel MTJ-CMOS Hybrid Latch and Flip-Flop

T. Ohsawa¹, S. Miura², H. Honjo², K. Kinoshita¹, S. Ikeda¹, T. Hanyu¹, H. Ohno¹, T. Endoh¹ (1.Tohoku Univ., 2.NEC Corp. (Japan))

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[M-6-4] Zero Area Overhead State Retention Flip Flop Utilizing Crystalline In-Ga-Zn Oxide Thin Film Transistor with Simple Power Control Implemented in a 32-bit CPU

N. Sjokvist^1,2, T. Ohmaru¹, K. Furutani¹, A. Isobe¹, N. Tsutsui¹, H. Tamura¹, W. Uesugi¹, T. Ishizu¹, T. Onuki¹, K. Ohshima¹, T. Matsuzaki¹, H. Mimura¹, A. Hirose¹, Y. Suzuki¹, Y. Ieda¹, T. Atsumi¹, Y. Shionoiri¹, K. Kato¹, G. Goto¹, J. Koyama¹, M. Fujita³, S. Yamazaki¹ (1.Semiconductor Energy Laboratory Co., Ltd., 2.Linkoping Univ., 3.Univ. of Tokyo (Japan))

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[M-7-1] Strategy of STT-MRAM Cell Design and Its Power Gating Technique for Low-Voltage and Low-Power Cache Memories

T. Ohsawa¹, S. Ikeda¹, T. Hanyu¹, H. Ohno¹, T. Endoh¹ (1.Tohoku Univ. (Japan))

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[M-7-2] Normally-off type Nonvolatile SRAM with perpendicular STT-MRAM cells and smallest number of transistors

C. Tanaka¹, K. Abe¹, H. Noguchi¹, K. Nomura¹, K. Ikegami¹, S. Fujita¹ (1.Toshiba Corporation (Japan))

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[M-7-3] Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell

H. Koike¹, T. Ohsawa¹, S. Miura², H. Honjo², S. Ikeda¹, T. Hanyu¹, H. Ohno¹, T. Endoh¹ (1.Tohoku Univ., 2.NEC Corp. (Japan))

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[M-7-4] Crystalline In-Ga-Zn-O FET-based Configuration Memory for Multi-Context Field-Programmable Gate Array Realizing Fine-Grained Power Gating

M. Kozuma¹, Y. Okamoto¹, T. Nakagawa¹, T. Aoki¹, M. Ikeda¹, T. Osada¹, Y. Kurokawa¹, T. Ikeda¹, N. Yamade¹, Y. Okazaki¹, H. Miyairi¹, M. Fujita², J. Koyama¹, S. Yamazaki¹ (1.Semiconductor Energy Laboratory Co., Ltd., 2.Univ. of Tokyo (Japan))

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[M-8-1] Properties and Application of Crystalline In-Ga-Zn-Oxide Semiconductor

S. Yamazaki¹ (1.Semiconductor Energy Lab. Corp., Ltd. (Japan))

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[M-8-2] A Normally Off Microcontroller Unit with an 84% Power Overhead Reduction Based On Crystalline In-Ga-Zn-Oxide Thin Film Transistors

K. Ohshima¹, H. Kobayashi¹, T. Nishijima¹, S. Yoneda¹, H. Tomatsu¹, K. Tsukida¹, K. Takahashi¹, T. Sato¹, K. Watanabe¹, R. Yamamoto¹, M. Kouzuma¹, T. Aoki¹, N. Yamade¹, Y. Ieda¹, H. Miyairi¹, T. Atsumi¹, Y. Shionoiri¹, K. Kato¹, Y. Maehashi¹, J. Koyama¹, S. Yamazaki¹ (1.Semiconductor Energy Laboratory Corp. Ltd. (Japan))

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[M-8-3] Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications

R. Nebashi¹, Y. Tsuji¹, H. Honjo¹, N. Sakimura^1,2, A. Morioka¹, K. Tokutome¹, S. Miura¹, S. Fukami², M. Yamanouchi², K. Kinoshita², T. Hanyu², T. Endoh², N. Kasai², H. Ohno², T. Sugibayashi¹ (1.NEC Corp., 2.Tohoku Univ. (Japan))

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