[P-2-12] Evaluation of Thin LSI Wafers by Capacitance-Time (C-t) Measurement for the Process Characterization of Three-Dimensional (3D) Integration

J.C. Bea¹、M. Murugesan¹、Y. Ohara¹、A. Noriki¹、H. Kino¹、K. W. Lee¹、T. Fukushima¹、T. Tanaka¹、M. Koyanagi¹ (1.Tohoku Univ.)

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-2-13] Low-Capacitance and Low-Loss Bond Pad Design using LC-Resonator Structure in CMOS Technology for RF and High-Speed Applications

C. Y. Lin¹、M. D. Ker^1,2 (1.National Chiao Tung Univ.(Taiwan)、2.I-Shou Univ.(Taiwan))

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-2-14] High-Q Embedded Spiral Inductor on Anodized Aluminum Substrate

C. H. Kim¹、J. H. Ahn¹、Y. J. Kim¹、Y. S. Kwon¹ (1.KAIST)

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-2-15] Influence of Magnetic Fieled on Permeability of Electroplating Permalloy for Micro Energy Harvesting Device

E. Kubo¹、N. Ooi¹、H. Aoki¹、D. Watanabe¹、J. H. Jeong¹、C. Kimura¹、T. Sugino¹ (1.Osaka Univ.)

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-3-1] Suppression of V_th Variability for n-MOSFET in Dual Oxide Formation Process

Y. Kamata¹、K. Shibusawa¹、K. Abe²、S. Sugawa²、A. Teramoto²、T. Ohmi² (1.OKI Semiconductor Miyagi Co., Ltd.(Japan)、2.Tohoku Univ.(Japan))

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-3-2] Rigorous Design of 20 nm Level SOI 4-T FinFETs for Low Standby Power by Extracting Parameters from the Pre-stage 50 nm Technology Node Devices

S. Cho¹、S. W. Kim¹、K. Endo²、S. O'uchi²、T. Matsukawa²、Y. Son¹、J. P. Kim¹、K. Sakamoto²、Y. Liu²、B. G. Park¹、M. Masahara² (1.Seoul National Univ.(Korea)、2.AIST(Japan))

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-3-3] Quantitative Analysis of Hump Effects of Multi-Gate MOSFETs for Low-Power Electronics

W. Lee¹、W. Y. Choi¹ (1.Sogang Univ.)

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-3-4] Investigation of Novel Si/SiGe Hetero Structures and Gate Induced Source Tunneling for Improvement of P-channel Tunnel FETs

H. G. Virani¹、R. B. Rao¹、A. Kottantharayil¹ (1.Indian Inst. Of Tech. Bombay)

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-3-5] Mecahnical stress evaluation of Si MOSFET structure using UV Raman spectroscopy measurements and calibrated TCAD simulation

A. Satoh¹、T. Tada²、V. Poborchii²、T. Kanayama²、H. Arimoto¹ (1.Fujitsu Microelectronics Ltd.(Japan)、2.AIST(Japan))

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード

[P-3-6] Recovery of CHC- and NBTI-induced Degradation on MOSFETs by using Different Annealing Treatments

C. H. Tu¹、S. Y. Chen¹、S. H. Chien¹、H. S. Huang¹、Z. W. Jhou²、S. Chou²、J. Ko² (1.National Taipei Univ. of Tech.(Taiwan)、2.UMC(Taiwan))

2009 International Conference on Solid State Devices and Materials |PDF ダウンロード