[D-7-3] Low Power and High Sensitivity MRAM Sensing Scheme with Body Biased Preamplifier

Takeaki Sugimura, Jun Deguchi, Hoon Choi, Takeshi Sakaguchi, Hyuckjae Oh, Takafumi Fukushima, Mitsumasa Koyanagi (1.Department of Bioengineering and Robotics, Tohoku University)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-8-1] A Spurious Suppression Technique for Fractional-N Frequency Synthesizers

Ryoichi Tachibana, Yutaka Shimizu, Shinichiro Ishizuka, Hideaki Masuoka (1.Corporate Research & Development Center, Toshiba Corporation, 2.Semiconductor Company, Toshiba Corporation)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-8-2] Design of Differential Transformer Balun and Its Application to CMOS LNA

Young Jae Lee, Jae Joon Kim, Hyun Kyu Yu (1.ETRI, Basic Research Laboratories, RF/Analog SoC Design Team, 2.MagnaChip Semiconductor, Wireless Team)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-8-3] Design of I-Q down-converter in CMOS for wireless network application

T.Hui Teo, Yong-Zhong Xiong (1.Institute of Microelectronics)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-8-4] Zero-Crosstalk Bus Line Structure for Global Interconnects in Si ULSI

Makoto Kimura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Kazuya Masu (1.Precision and Intelligence Laboratory, Tokyo Institute of Technology)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-9-1] Development of an Integrated RF Impedance Matching Device with LPF Function using a CoFeB Magnetic/Polyimide Dielectric Hybrid Thin-Film Coplanar-Line

H. Nakayama, T. Yamamoto, Y. Mizoguchi, T. Sato, K. Yamasawa, Y. Miura, Y. Miyake, M. Akie, Y. Uehara, M. Munakata, M. Yagi (1.Nagano National College of Technology, 2.Faculty of Engineering, Shinshu University, 3.Fujitsu Limited, 4.Energy Electronics Laboratory, Sojo University)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-9-2] A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT

Cheng-Hsiao Lai, Liang-Wei Lai, Ya-Chin King (1.Microelectronic Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing-Hua University)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-9-3] Neutron-induced Soft-Error Simulation Technology for Logic Circuits

Taiki Uemura, Yoshiharu Tosaka, Shigeo Satoh (1.Fujitsu Laboratories Ltd.)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-9-4] Mismatches under the Impact of Hot Carrier Stress in 0.15 μm Technology

S. Y. Chen, J. C. Lin, H. W. Chen, H. C. Lin, Z. W. Jhou, S. Chou, J. Ko, T. F. Lei, H. S. Haung (1.Institute of Mechatronics Engineering, National Taipei University of Technology, 2.Special Technology Division, United Microelectronics Corporation, 3.Department of Electronics Engineering, National Chiao Tung University)

2005 International Conference on Solid State Devices and Materials |PDF Download

[D-10-1] The High Voltage Anti-Trend

Chris Mangelsdorf (1.Analog Devices, K.K., Japan Design Center)

2005 International Conference on Solid State Devices and Materials |PDF Download