Oral presentation

[21a-C105-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Wed. Sep 21, 2022 9:00 AM - 12:15 PM C105 (C105)

Kentaro Kinoshita(Tokyo Univ. of Sci.), Satoshi Yamauchi(茨大)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

△ [21a-C105-1] Impacts of GeSbTe composition on the reset current of PCM/Selector stacked memory

〇Matsuzawa Yuya¹, Katono Kazuhiro¹, Fujii Shosuke¹, Fujimaki Takeshi¹ (1.KIOXIA)

9:15 AM - 9:30 AM

[21a-C105-2] The Effect of Hydrogen Impurities on Interfacial Magnetic Anisotropy Energy at Fe/MgO Structure in Magnetic Tunnel Junction

〇Takuya Nawa¹, Keisuke Morishita¹, Masaaki Araidai^1,2, Tetsuo Endoh^3,4,5, Kenji Shiraishi^1,2,3 (1.Graduate School of Engineering, Nagoya Univ., 2.IMass, Nagoya Univ., 3.cies, Tohoku Univ., 4.Graduate School of Engineering, Tohoku Univ., 5.RIEC, Tohoku Univ.)

9:30 AM - 9:45 AM

[21a-C105-3] Tantalum-oxide thin film formation by electrochemical oxidation method and its application to ReRAM cell formation: effect of water-drop-additions during oxidation

〇Naohito Miyata¹, Manabu Sueki¹, Yoshiaki Ishii¹, Masao Takahashi¹, Masahiro Moniwa¹ (1.Tokyo Univ. of Tecnology)

9:45 AM - 10:00 AM

[21a-C105-4] Design of nonvolatile SRAM using FinFETs for low-voltage operation

〇Osamu Yamazaki¹, Yusaku Shiotsu¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech)

10:00 AM - 10:15 AM

[21a-C105-5] Proposal of a new ultralow-voltage-retention SRAM (ULVR-SRAM) cell

〇Katsutoshi Ito¹, Yusaku Shiotsu¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

10:15 AM - 10:30 AM

[21a-C105-6] Power-gating performance of ultralow-voltage-retention SRAM for near-threshold-voltage operation

〇Taketo Kato¹, Yusaku Shiotsu¹, Syuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

10:45 AM - 11:00 AM

[21a-C105-7] Low resistivity Cu-layer deposition by selective-CVD used CuI as precursor

〇Gento Toyoda¹, Satoshi Yamauchi¹ (1.Ibaraki Univ.)

11:00 AM - 11:15 AM

△ [21a-C105-8] Electromigration in the intermetallic compound CuAl₂

〇Toshihiro Kuge^1,2, Yahagi Masataka^1,2, Koike Junichi¹ (1.Tohoku Univ., 2.JX Nippon Mining & Metals Corp.)

11:15 AM - 11:30 AM

[21a-C105-9] Formation and Evaluation of Ru Films for Fine Interconnect Application by Electroless Plating

〇Saida Ryota¹, Tomohiro Shimizu¹, Takeshi Ito¹, Shoso Shingubara¹ (1.Kansai Univ.)

11:30 AM - 11:45 AM

[21a-C105-10] Resistivity reduction of fine metal line by KrF excimer laser annealing

Yasutsugu Usami¹, 〇Kaname Imokawa¹, Ryoichi Nohdomi¹, Kouji Kakizaki¹, Hakaru Mizoguchi¹ (1.Gigaphoton Inc.)

11:45 AM - 12:00 PM

[21a-C105-11] Metal pattern formed by selective neutral copper plating on polyimide film

〇Yudai Hirano¹, Sugiura Osamu¹ (1.Chiba Inst of Tech.)

12:00 PM - 12:15 PM

[21a-C105-12] Warpage Suppression of Wafer Level Package for Heterogeneous Integration

〇Yusuke Araki Araki¹, Yuta Shiratori¹, Fumito Nakajima¹ (1.NTT Device Technology Labs.)

Oral presentation

[21p-C105-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Wed. Sep 21, 2022 1:30 PM - 4:30 PM C105 (C105)

Takeaki Yajima(Kyushu Univ.), Takahiro Mori(AIST)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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1:30 PM - 1:45 PM

[21p-C105-1] Validity of electron mobility of Si nMOSFETs at cryogenic temperature determined by a nonlinear model of surface roughness scattering

〇Kei Sumita¹, Min-Soo Kang¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.U. Tokyo)

1:45 PM - 2:00 PM

△ [21p-C105-2] Orientation Dependence of Effective Electron Mobility in Cryogenic MOSFET

〇Hiroshi Oka¹, Takumi Inaba¹, Shota Iizuka¹, Hidehiro Asai¹, Kouichi Fukuda¹, Kimihiko Kato¹, Takahiro Mori¹ (1.AIST)

2:00 PM - 2:15 PM

△ [21p-C105-3] Transient characteristics of 65-nm generation bulk transistors at 4.2 K operation

〇(M1)Tomohisa Miyao¹, Takahisa Tanaka¹, Itsuki Imanishi¹, Masayuki Ichikawa², Shuya Nakagawa², Hiroki Ishikuro², Toshitsugu Sakamoto³, Munehiro Tada³, Ken Uchida¹ (1.The Univ. of Tokyo, 2.Keio Univ., 3.Nanobridge Semiconductor)

2:15 PM - 2:30 PM

[21p-C105-4] A Study on Improvement of Output Characteristics of Tunnel FET by Pocket Structure

〇(M1)Naoyuki Onishi¹, Riku Fujii¹, Koki Endo¹, Yan Wu¹, Yoshihiro Takahashi¹ (1.Nihon Univ.)

2:30 PM - 2:45 PM

△ [21p-C105-5] Characteristics of Steep SS "Dual Gate type PN-Body Tied SOI-FET" N/PMOS

〇(M1)Haruki Yonezaki¹, Jiro Ida¹, Takayuki Mori¹ (1.Kanazawa Inst. of Tech.)

2:45 PM - 3:00 PM

[21p-C105-6] Neuron Operation by Using Single “PN-Body Tied SOI-FET”

〇Takayuki Mori¹, Jiro Ida¹ (1.Kanazawa Inst. of Tech.)

3:15 PM - 3:30 PM

[21p-C105-7] Hetero-oriented Ge complementary FET (CFET) through layer transfer technology

〇WENHSIN CHANG¹, X. R. Yu^2,3, W. F. Wu², Y. J. Lee², Y. H. Wang³, Tatsuro Maeda¹ (1.AIST, 2.TSRI, 3.NCKU)

3:30 PM - 3:45 PM

▲ [21p-C105-8] Highly-asymmetric-strain (110) SiGe-on-insulator pMOSFETs with extremely-thin body channels down to 3.2 nm fabricated by using Ge condensation technique

〇CHIATSONG CHEN¹, Xueyang Han¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. of Tokyo)

3:45 PM - 4:00 PM

[21p-C105-9] Accurate Evaluation of Interface Trap Density at InAs MOS Interfaces by C-V Measurements at Low Temperatures

〇(M2)Ryohei Yoshizu¹, Kei Sumita¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. Tokyo)

4:00 PM - 4:15 PM

△ [21p-C105-10] Study of the rate of insulator transition in VO₂ three terminal device

〇Satoshi Hamasuna¹, Satya Prakash Pati¹, Takeaki Yajima¹ (1.Kyushu Univ.)

4:15 PM - 4:30 PM

[21p-C105-11] Optimal Design of Multilayer Si Nanosheet Thermoelectric Generation Devices

〇Yuma Miyake¹, Katsuki Abe¹, Motohiro Tomita¹, Takeo Matsuki², Takanobu Watanabe¹ (1.Waseda Univ., 2.AIST)

Oral presentation

[22a-A102-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

Thu. Sep 22, 2022 9:00 AM - 11:45 AM A102 (A102)

Daniel Moraru(静大)

△：Presentation by Applicant for JSAP Young Scientists Presentation Award
▲：English Presentation
▼：Both of Above
No Mark：None of Above

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9:00 AM - 9:15 AM

[22a-A102-1] Direct observation of electron capture processes in amphoteric defect states achieved by charge pumping in individual defects at MOS interface (4) -Lattice relaxation-

〇Toshiaki Tsuchiya¹, Masahiro Hori¹, Yukinori Ono¹ (1.Shizuoka Univ.)

9:15 AM - 9:30 AM

[22a-A102-2] Direct observation of electron capture processes in amphoteric defect states achieved by charge pumping in individual defects at MOS interface (5) -Discrimination between Type 4 & 5-

〇Toshiaki Tsuchiya¹, Masahiro Hori¹, Yukinori Ono¹ (1.Shizuoka Univ.)

9:30 AM - 9:45 AM

[22a-A102-3] Study of tunneling currents via energy states in the depletion layer of Si nano-Esaki diodes

〇yuta tamura¹, Moraru Daniel¹ (1.RIE, Shizuoka Univ)

9:45 AM - 10:00 AM

[22a-A102-4] Study of backgate effect voltage on single-electron tunneling in co-doped Si nano-transistors

〇Tsutomu Kaneko¹, Jupalli Taruna Teja¹, Moraru Daniel¹ (1.RIE, Shizuoka Univ)

10:00 AM - 10:15 AM

△ [22a-A102-5] Evaluating the Temperature Dependence of Charge Noise in a pMOS Si Quantum Dot

〇Kazuma Nakagoe¹, Ryuta Tsuchiya², Toshiyuki Mine², Digh Hisamoto², Hiroyuki Mizuno², Raisei Mizokuchi¹, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech, 2.R&D Group, Hitachi Ltd.)

10:15 AM - 10:30 AM

[22a-A102-6] Time control operation of a silicon hole spin in physically defined quantum dots at elevated temperatures

〇Takumi Yoshikawa¹, Yusaku Suzuki¹, Sayyid Ibad¹, Shimpei Nishiyama^1,2, Kimihiko Kato², Yongxun Liu², Shigenori Murakami², Takahiro Mori², Mizokuchi Raisei¹, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech, 2.AIST)

10:30 AM - 10:45 AM

△ [22a-A102-7] S-parameter measurement of a quantum dot and matching circuit design for improvement of RF reflectometry

〇(M1)Ryo Matsuda¹, Jun Kamioka¹, Raisei Mizokuchi¹, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech)

10:45 AM - 11:00 AM

[22a-A102-8] Contact Pad Designs of Semiconductor Qubit Devices for Reducing On-chip Microwave Crosstalk

〇Kaito Tomari^1,2, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech., 2.Nikon Corp.)

11:00 AM - 11:15 AM

△ [22a-A102-9] Cryogenic active inductors toward dense spin qubit readout circuits

〇Tokio Futaya¹, Raisei Mizokuchi¹, Jun Kamioka¹, Jun Yoneda¹, Tetsuo Kodera¹ (1.Tokyo Tech.)

11:15 AM - 11:30 AM

[22a-A102-10] Impact of buried nanomagnet technology on one-dimensionally integrated silicon qubits

〇Shota Iizuka¹, Kimihiko Kato¹, Atsushi Yagishita¹, Hidehiro Asai¹, Tetsuya Ueda¹, Hiroshi Oka¹, Junichi Hattori¹, Tsutomu Ikegami¹, Koichi Fukuda¹, Takahiro Mori¹ (1.AIST)

11:30 AM - 11:45 AM

△ [22a-A102-11] Quantum Current Source Realized by Surface Acoustic Wave Pulses

〇Shunsuke Ota^1,2, Junliangn Wang³, Hermann Edlbauer³, Baptiste Jadot³, Pierre-Andre Mortemousque^3,4, Aymeric Richard³, Yuma Okazaki², Shuji Nakamura², Arne Ludwig⁵, Andreas D. Wieck⁵, Matias Urdampilleta³, Tristan Meunier³, Tetsuo Kodera¹, Nobu-Hisa Kaneko², Christopher Bauerle³, Shintaro Takada² (1.Tokyo Tech., 2.AIST, 3.Inst. Neel, 4.UGA, 5.RUB)

Sessions

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[21a-C105-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [21a-C105-1] Impacts of GeSbTe composition on the reset current of PCM/Selector stacked memory

[21a-C105-2] The Effect of Hydrogen Impurities on Interfacial Magnetic Anisotropy Energy at Fe/MgO Structure in Magnetic Tunnel Junction

[21a-C105-3] Tantalum-oxide thin film formation by electrochemical oxidation method and its application to ReRAM cell formation: effect of water-drop-additions during oxidation

[21a-C105-4] Design of nonvolatile SRAM using FinFETs for low-voltage operation

[21a-C105-5] Proposal of a new ultralow-voltage-retention SRAM (ULVR-SRAM) cell

[21a-C105-6] Power-gating performance of ultralow-voltage-retention SRAM for near-threshold-voltage operation

[21a-C105-7] Low resistivity Cu-layer deposition by selective-CVD used CuI as precursor

△ [21a-C105-8] Electromigration in the intermetallic compound CuAl₂

[21a-C105-9] Formation and Evaluation of Ru Films for Fine Interconnect Application by Electroless Plating

[21a-C105-10] Resistivity reduction of fine metal line by KrF excimer laser annealing

[21a-C105-11] Metal pattern formed by selective neutral copper plating on polyimide film

[21a-C105-12] Warpage Suppression of Wafer Level Package for Heterogeneous Integration

[21p-C105-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[21p-C105-1] Validity of electron mobility of Si nMOSFETs at cryogenic temperature determined by a nonlinear model of surface roughness scattering

△ [21p-C105-2] Orientation Dependence of Effective Electron Mobility in Cryogenic MOSFET

△ [21p-C105-3] Transient characteristics of 65-nm generation bulk transistors at 4.2 K operation

[21p-C105-4] A Study on Improvement of Output Characteristics of Tunnel FET by Pocket Structure

△ [21p-C105-5] Characteristics of Steep SS "Dual Gate type PN-Body Tied SOI-FET" N/PMOS

[21p-C105-6] Neuron Operation by Using Single “PN-Body Tied SOI-FET”

[21p-C105-7] Hetero-oriented Ge complementary FET (CFET) through layer transfer technology

▲ [21p-C105-8] Highly-asymmetric-strain (110) SiGe-on-insulator pMOSFETs with extremely-thin body channels down to 3.2 nm fabricated by using Ge condensation technique

[21p-C105-9] Accurate Evaluation of Interface Trap Density at InAs MOS Interfaces by C-V Measurements at Low Temperatures

△ [21p-C105-10] Study of the rate of insulator transition in VO₂ three terminal device

[21p-C105-11] Optimal Design of Multilayer Si Nanosheet Thermoelectric Generation Devices

[22a-A102-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[22a-A102-1] Direct observation of electron capture processes in amphoteric defect states achieved by charge pumping in individual defects at MOS interface (4) -Lattice relaxation-

[22a-A102-2] Direct observation of electron capture processes in amphoteric defect states achieved by charge pumping in individual defects at MOS interface (5) -Discrimination between Type 4 & 5-

[22a-A102-3] Study of tunneling currents via energy states in the depletion layer of Si nano-Esaki diodes

[22a-A102-4] Study of backgate effect voltage on single-electron tunneling in co-doped Si nano-transistors

△ [22a-A102-5] Evaluating the Temperature Dependence of Charge Noise in a pMOS Si Quantum Dot

[22a-A102-6] Time control operation of a silicon hole spin in physically defined quantum dots at elevated temperatures

△ [22a-A102-7] S-parameter measurement of a quantum dot and matching circuit design for improvement of RF reflectometry

[22a-A102-8] Contact Pad Designs of Semiconductor Qubit Devices for Reducing On-chip Microwave Crosstalk

△ [22a-A102-9] Cryogenic active inductors toward dense spin qubit readout circuits

[22a-A102-10] Impact of buried nanomagnet technology on one-dimensionally integrated silicon qubits

△ [22a-A102-11] Quantum Current Source Realized by Surface Acoustic Wave Pulses

Authenticate

Sessions

13 Semiconductors » 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[21a-C105-1~12] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [21a-C105-1] Impacts of GeSbTe composition on the reset current of PCM/Selector stacked memory

△ [21a-C105-8] Electromigration in the intermetallic compound CuAl2

[21p-C105-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [21p-C105-2] Orientation Dependence of Effective Electron Mobility in Cryogenic MOSFET

△ [21p-C105-3] Transient characteristics of 65-nm generation bulk transistors at 4.2 K operation

△ [21p-C105-5] Characteristics of Steep SS "Dual Gate type PN-Body Tied SOI-FET" N/PMOS

▲ [21p-C105-8] Highly-asymmetric-strain (110) SiGe-on-insulator pMOSFETs with extremely-thin body channels down to 3.2 nm fabricated by using Ge condensation technique

△ [21p-C105-10] Study of the rate of insulator transition in VO2 three terminal device

[22a-A102-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

△ [22a-A102-5] Evaluating the Temperature Dependence of Charge Noise in a pMOS Si Quantum Dot

△ [22a-A102-7] S-parameter measurement of a quantum dot and matching circuit design for improvement of RF reflectometry

△ [22a-A102-9] Cryogenic active inductors toward dense spin qubit readout circuits

△ [22a-A102-11] Quantum Current Source Realized by Surface Acoustic Wave Pulses

Authenticate

△ [21a-C105-8] Electromigration in the intermetallic compound CuAl₂

△ [21p-C105-10] Study of the rate of insulator transition in VO₂ three terminal device