[B-7-4] Mitigation of CMOS Variability with Metal Gate

J. W. Yang¹、C. S. Park¹、H. R. Harris¹、C. E. Smith¹、H. Adhikari¹、J. Huang¹、D. Heh¹、P. Majhi¹、R. Jammy¹ (1.SEMATECH, USA)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-8-1] Simulation of Material and Strain Engineering of Tunneling Field-Effect Transistor with Subthreshold Swing below 60mV/decade (Invited)

G. Samudra¹、Y. C. Yeo¹、C. H. Heng¹、E. H. Toh¹、L. Yang¹ (1.National Univ. of Singapore, Singapore)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-8-2] Understanding the Effect of Laser Anneal on LSTP 45nm Node MOS Transistor Electrical Parameters

A. Cros¹、S. Renard¹、M. Bidaud¹、R. Ranica¹、G. Ribes¹、E. Josse¹、B. Dumont¹、R. Beneyton¹、K. Barla¹、M. Haond¹、H. Brut¹ (1.STMicroelectronics, France)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-8-3] N-Channel MOSFETs with Embedded Silicon-Carbon Source/Drain Stressors Formed using Novel Cluster-Carbon Implant and Excimer Laser-Induced Solid Phase Epitaxy

S. M. Koh¹、K. Sekar²、W. Krull²、X. Wang³、G. Samudra¹、Y. C. Yeo¹ (1.National Univ. of Singapore, Singapore、2.SemEquip Inc., USA、3.Singapore Inst. of Manufacturing Tech., Singapore)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-8-4] Steeper Indium Halo Formation of nMOSFET by Reducing Interstitial Supersaturation with Flash Lamp pre-Annealing and its Modeling with Atomistic Kinetic Monte Carlo

T. Sawada²、N. Zographos⁴、H. Yoshimura¹、T. Sanuki¹、T. Ito¹、T. Itani¹、H. Aikawa¹、O. Fujii¹、N. Kariya³、M. Oulmane⁴、R. Gull⁴、Y. Akiyama³、M. Ikeda³、M. Iwai¹、F. Matsuoka¹ (1.Toshiba Corp.、2.Toshiba Information Systems Tech. Inc.、3.NEC Electronics Corp., Japan、4.Synopsys Switzerland LLC, Switzerland)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-9-1] A Study on Very High Performance Novel Balanced FD-SOI CMOSFETs on Si(110) using Accumulation Mode Device Structure for RF Analog Circuits

W. Cheng¹、A. Teramoto¹、C. Tye¹、R. Kuroda¹、S. Sugawa¹、T. Ohmi¹ (1.Tohoku Univ., Japan)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-9-2] Comparison of Plasma Doping with Implant for High Performance SOI CMOS Fabrication

K. L. Lee¹、I. Lauer¹、J. Li¹、P. Porshnev²、P. Ronsheim¹、J. Gardner¹、P. Kozlowski¹、K. Santhanam²、M. Foad²、D. G. Park¹ (1.IBM、2.Applied Materials Inc., USA)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-9-3] Evaluation of Threshold-Voltage Variation in Silicon on Thin BOX (SOTB) CMOS and its Impact on Decreasing Standby Leakage Current

N. Sugii¹、R. Tsuchiya¹、T. Ishigaki¹、Y. Morita¹、H. Yoshimoto¹、T. Iwamatsu²、H. Oda²、Y. Inoue²、T. Hiramoto³、S. Kimura¹ (1.Hitachi, Ltd.、2.Renesas Tech. Corp.、3.Univ. of Tokyo, Japan)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-9-4] Effect of Poly/SiON Gate Stack Combined with Thin BOX and Ground Plane for Low Vth and Analog Applications of FDSOI Devices

C. Fenouillet-Beranger^1,2、P. Perreau^1,2、S. Kohler¹、F. Arnaud¹、M. Cassé²、X. Garros²、C. Laviron^1,2、P. Garnier¹、P. Rivallin²、D. Chanemougame¹、R. Beneyton¹、A. Torres^1,2、D. Barge¹、N. Cherault¹、P. Gouraud¹、F. Leverd¹、E. Deloffre¹、M. Gros-Jean¹、N. Loubet¹、F. Abbate¹、M. Fournier¹、M. Gattefait¹、J. D. Chapon¹、B. Le-Gratiet¹、M. Gregoire¹、J. Bienacel¹、P. Gros¹、N. Kubler¹、G. Guierleo¹、C. Mezzomo¹、M. Marin¹、C. Leyris¹、R. Pantel¹、O. Faynot²、C. Buj²、F. Andrieu²、S. Barnola²、T. Salvetat²、S. Denorme¹、S. Deleonibus²、T. Skotnicki¹ (1.STMicroelectronics、2.CEA-LETI/MINATEC, France)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード

[B-9-5] Characteristics of Thin-Body <100> Channel SOI MOSFETs by using Two Step Elevated Silicon Eptaxtial Process

K. Ishikawa¹、T. Iwamatsu¹、T. Terada¹、H. Oda¹、Y. Inoue¹ (1.Renesas Tech. Corp., Japan)

2008 International Conference on Solid State Devices and Materials |PDF ダウンロード