2015 International Conference on Solid State Devices and Materials

Sep 27, 2015 - Sep 30, 2015
Sapporo Convention Center, Sapporo, Japan

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894 results (661 - 670)

[PS-3-1] Discrete Dopant Impact on the 7 nm Nanowire Transistor Performance

^○X. Wang¹, Y. Wang², C. Riddet³, E. Towie³, B. Cheng³, X. Liu², A. Asenov^1,3 (1.Univ. of Glasgow, 2.Peking Univ., 3.Gold Standard Simulations Ltd.(UK))

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[PS-3-2] Proposal of Tunneling and Diffusion Current Hybrid MOSFET

^○K. Furukawa¹, R. Kuroda¹, T. Suwa¹, K. Hashimoto¹, A. Teramoto¹, S. Sugawa¹ (1.Tohoku Univ.(Japan))

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[PS-3-3] RF Characteristics of Poly-Si TFTs with HfO₂ Gate Dielectric Fabricated by Microwave Annealing

J. J. Tsai¹, ^○H. H. Hu¹ (1.National Taipei Univ. of Tech.(Taiwan))

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[PS-3-4] Trap-Assisted Tunneling Effects on Gate-Induced Drain Leakage in Silicon-Germanium Channel pFET

^○V. A. Tiwari¹, A. Scholze², R. Divakaruni², D. R. Nair¹ (1.Indian Inst. of Tech. Madras, 2.IBM Semiconductor Res. and Development Center(India))

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[PS-3-5] Low Frequency Noise and Mobility Correlation from RT to Low Temperatures for n-Channel Ge MOSFETs

^○S. Ghosh¹, P. Bhatt¹, Y. Tiwari¹, S. Lodha¹ (1.IIT Bombay(India))

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[PS-3-6] Comparison of Gate Structures of P-channel Poly-Si Nanowire Trench Ultra-thin Channel Juntionless Field-Effect Transistors

^○Y. C. Wu¹, K. W. Lin¹, M. S. Yeh¹, Y. R. Lin¹, M. H. Wu¹, Y. H. Lin² (1.National Tsing Hua Univ., 2.National United Univ.(Taiwan))

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[PS-3-7] 1/f Noise Performances and Noise Sources of Accumulation Mode Si(100) n-MOSFETs

^○P. Gaubert¹, A. Teramoto¹, S. Sugawa¹ (1.Tohoku Univ.(Japan))

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[PS-3-8] ON Current Enhancement of Nanowire Schottky Barrier Tunnel FET

^○K. Takei¹, S. Hashimoto¹, J. Sun¹, X. Zhang¹, S. Asada¹, T. Xu¹, T. Wakamizu¹, T. Matsukawa², M. Masahara², T. Watanabe¹ (1.Waseda Univ., 2.AIST(Japan))

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[PS-3-9] Novel 5-State Latch Using Double-Peak Negative Differential Resistance (NDR) and Standard Ternary Inverter (STI)

^○S. Shin¹, K. R. Kim¹ (1.UNIST(Korea))

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[PS-3-10] Impacts of Threshold Voltage Design for Monolithic 3D 6T SRAM with Si and InGaAs-n/Ge-p Devices considering Interlayer Coupling

^○K. C. Yu¹, C. H. Yu¹, V. P. H. Hu¹, P. Su¹, C. T. Chuang¹ (1.National Chiao Tung Univ.(Taiwan))

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894 results (661 - 670)