[PS-2-5] Local Stress Effect Due to Operation-Heating-Induced Adhesive Expansion on Transistor Performances in 3D IC

^○H. Kino¹, H. Hashiguchi¹, S. Tanikawa¹, Y. Sugawara¹, S. Ikegaya¹, T. Fukusima¹, M. Koyanagi¹, T. Tanaka¹ (1.Tohoku Univ.(Japan))

2015 International Conference on Solid State Devices and Materials |PDF Download

[PS-2-6] Combined Surface-Activated Bonding Technique for Low-Temperature Hydrophilic Wafer Bonding with Interfacial Water Management

^○R. He¹, M. Fujino¹, A. Yamauchi², T. Suga¹ (1.Univ. of Tokyo, 2.Bondtech Co., Ltd.(Japan))

2015 International Conference on Solid State Devices and Materials |PDF Download

[PS-2-7] Transient Liquid-Phase Sintering using Tin and Silver Powder Mixture for Die Bonding

^○M. Fujino¹, H. Narusawa¹, Y. Kuramochi¹, E. Higurashi¹, T. Suga¹, T. Shiratori², M. Mizukoshi³ (1.Univ. of Tokyo, 2.ALPHA DESIGN CO., LTD., 3.SYNDEO(Japan))

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[PS-2-8] A Novel Hybrid Strategy of via-first Bare TSVs for Enhanced Signal Integrity in 3-D Integrated Systems

^○R. Fang¹, X. Sun¹, M. Miao², Y. Jin¹ (1.Peking Univ., 2.Beijing Information Sci.&Tech. Univ.(China))

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[PS-2-9] Capacitance Characteristics of Low-k Low-Cost CVD Grown Polyimide Liner for High-Density Cu-TSVs in 3D-LSI

^○M. Mariappan¹, J. C. Bea¹, T. Fukushima¹, H. Hashimoto¹, K. W. Lee¹, M. Koyanagi¹ (1.Tohoku Univ.(Japan))

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[PS-2-10] Improving Step Coverage of PVD Barrier/Seed through Bias Power Alternation for High Aspect Ratio TSVs

^○S. Yang¹, W. Cheng¹, H. Wu¹, C. Song^1,2, W. Zhang^1,2 (1.National Center for Advanced Packaging Co., LTD., 2.Inst. of Microelectronics, Chinease Academy of Sci.(China))

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[PS-2-11] Thermal Mechanical Behavior of TSVs with WN/Ni as Barrier/Seed Layer System for 2.5D Integration

^○X. M. Jing¹ (1.Natianal Center for Advanced Packaging(China))

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[PS-2-12] Electroless Nickel Barrier/Seed Layer Deposition on Dielectric Liners for Advanced Cu-TSV Applications

^○T. Fukushima¹, K. Taniguchi², S. Watariguchi², M. Murugesan¹, C. Nagai¹, A. Nakamura¹, H. Hiroyuki¹, J. Bea¹, T. Tanaka¹, M. Koyanagi¹, K. Lee¹ (1.Tohoku Univ., 2.Meltex Inc.(Japan))

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[PS-2-13] A Novel Low Temperature (<500°C) and Low-κ (3.8) Boron Nitride PECVD Offset Spacer Featuring 3D VLSI Integration

^○C. M. V. Lu^1,2, C. Bout¹, C. Fenouillet Beranger¹, A. Roule¹, M. P. Samson^1,2, B. Previtali¹, C. Arvet^1,2, A. Michallet^1,2, N. Rochat¹, S. Favier^1,2, R. Kachtouli¹, V. Loup¹, BessonP. ^1,2, M. Garcia Barros^1,2, N. Posseme¹, F. Pierre¹, P. Maury², D. Benoit², P. Batude¹, M. Vinet¹, T. Skotnicki² (1.CEA-LETI, MINATEC Campus, 2.STMicroelectronics(France))

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[PS-2-14] Impact and Improvement of Resistor Process Variation on RF Passive Circuit Design in Integrated Passive Devices (IPD) Technology

^○Y. C. Chang^1,2, P. Y. Wang¹, S. H. Hsu¹, Y. T. Chang³, C. K. Chen³, D. C. Chang² (1.National Tsing Hua Univ., 2.National Chip Implementation Center, National Applied Res. Labs., 3.Bureau of Standards, Metrology and Inspection, MOEA(Taiwan))

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