[PC-10-1] Thin-SOI Process Using Bonding and Etch-Back Method without Epitaxial Growth

Hideyuki Unno, Kazuo Imai (1.NTT LSI Laboratories)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-2] X-Ray Topographic Investigations on Bonded Silicon on Insulator (BESOI) Wafers

Takao ABE, Hiroshi TAKENO, Koetsu SAWAI, Toshihiko TAKAMA (1.Shin-Etsu Handotai, 2.Faculty of Engineering, Hokkaido University)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-3] Advanced Quality in Epitaxial Layer Transfer by Bond and Etch-Back of Porous Si

Nobuhiko SATO, Kiyofumi SAKAGUCHI, Kenji YAMAGATA, Yasutomo FUJIYAMA, Jun NAKAYAMA, Takao YONEHARA (1.Device Development Center, R&D Headquarters, Canon Inc.)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-4] Partially Bonded SOI Substrates for Intelligent Power ICs

Hiroaki Kikuchi Kenichi Arai (1.ULSI Device Development Laboratories NEC Corporation)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-5] SOI LIGBT Structure with the Collector-Short Region for Improved Latch-Up Performance

Hitoshi Sumida, Atsuo Hirabayashi (1.Advanced Device Technology Laboratory, Fuji Electric Corporate R&D, Ltd.)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-6] Comparison of Standard and Low-Dose SIMOX Substrates for 0.15μm SOI MOSFET Applications

Hans-Oliver JOACHIM, Yasuo YAMAGUCHI, Takeshi FUJINO, Takaaki KATO, Yasuo INOUE, Tadashi HIRAO (1.ULSI Laboratory, Mitsubishi Electric Corporation)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-7] Advantages of Ultra-Thin SIMOX/CMOS Based on Well-Established 0.8μm Mass-Production Technologies for Low Power 1V PLL Circuits

O. Tsuboi, S. Warashina, K. Sukegawa, S. Kawai, S. Kawamura, S. Sekine, K. Takada, Y. Suzuki (1.CMOS Process Development Div., Analog LSI Development Div. Fujitsu Ltd.)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-8] Analysis of Si-Ge Source Structure in 0.15 μm SOI MOSFETs Using Two-Dimensional Device Simulation

Osamu ARISUMI, Kazuya MATSUZAWA, Naoyuki SHIGYO, Mamoru TERAUCHI, Akira NISHIYAMA, Makoto YOSHIMI (1.ULSI Research Laboratories, R & D Center, Toshiba Corporation)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-9] Modeling on the Channel-To-S/D Capacitance and the Short Channel Effect for 0.1μm Fully Depleted SOI-MOSFET

Risho Koh, Haruo Kato, Hiroshi Matsumoto (1.Microelectronics Res. Labs., ULSI Device Development Labs. NEC Corp.)

1995 International Conference on Solid State Devices and Materials |PDF Download

[PC-10-10] An Accurate Impact Ionization Current Model for LDD SOI MOSFETs

S. Pidin, N. Terao, T. Matsumoto, Y. Inoue, M. Koyanagi (1.Department of Machine Intelligence and System Engineering, Faculty of Engineering, Tohoku University, 2.Mitsubishi Electric Corporation, ULSI Laboratory)

1995 International Conference on Solid State Devices and Materials |PDF Download

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