[C-8-3] Gate Overlapped Raised Extension Structure (GORES) MOSFET by Using In-situ Doped Selective Si Epitaxy

Y. Tateshita, T. Imoto, Y. Kikuchi, J. Wang, T. Kataoka, Y. Miyanami, H. Ikeda, S. Fujita, T. Landin, C. Arena, H. Iwamoto, T. Ohno, T. Kobayashi, M. Saito, S. Kadomura, N. Nagashima (1.Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation, 2.ASM America Inc.)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-8-4] A Double-Gate device architecture optimization for sub-45nm digital CMOS technologies using cell-based timing analysis

R. Surdeanu, G. Doornbos, R. Ng, P. Christie, V.H. Nguyen, B.J. Pawlak, J.J.G.P. Loo, M.J.H.van Dal, Y.V. Ponomarev (1.Philips Research Leuven)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-9-1] Dopant Redistribution at Nickel Silicide/Silicon Interface

Takashi Yamauchi, Atsuhiro Kinoshita, Kazuya Ohuchi, Koichi Kato (1.Advanced LSI Technology Laboratory, Corporate Research & Development Center, Toshiba Corporation, 2.SoC Research & Development Center, Semiconductor Company, Toshiba Corporation)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-9-2] Integration of ultra shallow junctions in PVD TaN nMOS transistors with Flash Lamp Annealing

S. Severi, K. De Meyer, B. J. Pawlak, R. Duffy, C. Kerner, S. McCoy, J. Gelpey, T. Selinger, L-A Ragnarsson, P. P. Absil, M. Jurczak, S. Biesemans (1.IMEC, 2.Katholieke Universiteit. Leuven, ESAT-INSYS, 3.Philips Research Leuven, 4.Mattson Technology Canada)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-9-3] Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes

Guk-Hyon Yon, Soo-Jin Hong, Gyoung Ho Buh, Tai-su Park, Yu Gyun Shin, U-In Chung, Joo-Tae Moon (1.Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-9-4] Function of Phase Switch Layer for Ultra Shallow Junction Formation by Green Laser Annealing

Akira Matsuno, Kentaro Shibahara (1.Reseach Center for Nanodevices and Systems, Hiroshima University, 2.Phoeton Corp.)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-10-1] Analysis of the Origin of the Threshold Voltage Change Induced by Impurity in Fully Silicided NiSi/SiO2 gate stacks

Kenzo Manabe, Kensuke Takahashi, Takashi Hase, Nobuyuki Ikarashi, Makiko Oshida, Toru Tatsumi, Hirohito Watanabe (1.System Devices Research Laboratories, NEC Corporation)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-10-2] Realization of A Metal Split Gate By Gate Full Ni-Silicidation Process For MOSFET RF/Analog Applications

Jun Yuan, Jason C. S. Woo (1.Electrical Engineering Department, University of California)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-10-3] Stress voltage polarity dependent threshold voltage shift behavior of ultrathin Hafnium oxide gated pMOSFET with TiN electrode

Hokyung Park, Rino Choi, Byoung Hun Lee, Chadwin D. Young, Man Chang, Jack C. Lee, Hyunsang Hwang (1.Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, 2.SEMATECH, 3.IBM Assignee, 4.Advanced Materials Research Center, The University of Texas at Austin)

2005 International Conference on Solid State Devices and Materials |PDF Download

[C-10-4] Highly Manufacturable Hf-silicate Technology with Optimized Composition for Gate-First Metal Gate CMOSFET

S.C. Song, S.H. Bae, J.H. Sim, G. Bersuker, Z. Zhang, P. Kirsch, P. Majhi, N. Moumen, P. Zeitzoff, B.H. Lee (1.SEMATECH, 2.IBM assignee, 3.Texas Instruments assignee, 4.Intel assignee)

2005 International Conference on Solid State Devices and Materials |PDF Download