[H-1-4] Sub-30 nm Strained P-Channel FinFETs with Condensed SiGe Source/Drain Stressors

Kian-Ming Tan, Tsung-Yang Liow, Rinus T. P. Lee, King-Jien Chui, Chih-Hang Tung, N. Balasubramanian, Ganesh S. Samudra, Won-Jong Yoo, Yee-Chia Yeo (1.Silicon Nano Device Lab., Dept of Electrical and Computer Engineering, National University of Singapore, 2.Institute of Microelectronics)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-1-5] Evaluating Strained/Relaxed-Ge, Strained-Si, Strained-SiGe For Future Nanoscale p-MOSFETs

Tejas Krishnamohan, Donghyun Kim, Christoph Jungemann, Yoshio Nishi, Krishna C. Saraswat (1.Department of Electrical Engineering, Stanford University, 2.University of the Armed Forces)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-2-1] Potential of and Issues with Multiple-Stressor Technology (MST) in High-Performance 45nm Generation Devices

T. Miyashita, A. Hatada, Y. Shimamune, T. Owada, N. Tamura, T. Aoyama, S. Satoh (1.Fujitsu Laboratories Ltd., 2.Fujitsu Limited.)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-2-2] Large Reduction in Standby Power Consumption Achieved with Stress-controlled SRAM Layout

H. Kudo, K. Ishikawa, R. Tanabe, H. Fukkutome, Y. Mishima, S. Satou, T. Sugii, F. Kihara, M. Okamoto, M. Yoshimura, T. Sugimachi, H. Hashimoto, M. Ohtsuki (1.FUJITSU LABOTARORIES LIMITED, 2.FUJITSU LIMITED)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-2-3] Layout Independent Transistor with Stress-controlled and Highly Manufacturable STI Process

K. Horita, M. Ishibashi, H. Umeda, T. Kawahara, T. Ikeda, T. Yamashita, T. Kuroi, Y. Inoue (1.Process Technology Development Div., Renesas Technology Corp.)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-2-4] A Full Analytical Model to evaluate Strain Induced by CESL on MOSFET Performances

F. Payet, F. Boeuf, C. Ortolland, T. Skotnicki (1.STMicroelectronics, 2.Philips Semiconductors)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-2-5] 56% pMOSFETs Drive Current Enhancement from Optimized Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS

K. H. Lee, C. T. Huang, W. H. Hung, L. S. Jeng, S. F. Ting, M. L. Tseng, J. C. Wu, T. M. Shen, Osbert Cheng, C. W. Liang (1.United Microelectronics Corp. (UMC), CRD Logic Division)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-7-1] Suppressed short-channel effect of DG-MOSFET and its modeling

Hideki Oka, Ryo Tanabe, Norio Sadachika, Akihiro Yumisaki, Mitiko Miura-Mattausch (1.Fujitsu Laboratories Ltd., 2.Graduate School of Advanced Sciences of Matter, Hiroshima University)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-7-2] A Continuous, Explicit Drain-Current Model for Asymmetric Undoped Double-Gate MOSFETs

Z. M. Zhu, X. Zhou, K. Chandrasekaran, G. H. See, S. C. Rustagi (1.School of Electrical and Electronic Engineering, Nanyang Technological University, 2.Institute of Microelectronics)

2006 International Conference on Solid State Devices and Materials |PDF Download

[H-7-3] Surface-Potential-Based MOS-Varactor Model for RF Applications

M. Miyake, N. Sadachika, D. Navarro, Y. Mizukane, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, S. Miyamoto (1.Graduate School of Advanced Sciences of Matter, 2.Research Center for Nanodevices and Systems, Hiroshima University, 3.Semiconductor Technology Academic Research Center)

2006 International Conference on Solid State Devices and Materials |PDF Download

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