[J-2-1] Comprehensive Investigation of Self-Heating Effect (SHE) in Nanoscale Planar and Fin FETs: Impacts of Device Parameters on SHE and Analog Performance Optimization

T. Takahashi^1,2, T. Matsuki³, T. Shinada³, Y. Inoue³, K. Uchida^1,2 (1.Keio Univ., 2.JST-CREST, 3.AIST (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-2-2] Improvement of S-factor Method for Evaluation of MOS Interface State Density

W.–L. Cai^1,2, M. Takenaka^1,2, S. Takagi^1,2 (1.Univ. of Tokyo, 2.JST-CREST (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-2-3] Effective Work Function Shift Induced by TiN Sacrificial Metal Gates as a Function of Their Thickness and Composition in 14nm NMOS devices

C. Suarez-Segovia^1,2, P. Caubet¹, V. Joseph¹, O. Gourhant¹, G. Romano¹, F. Domengie¹, G. Ghibaudo² (1.STMicroelectronics, 2.IMEP-LAHC (France))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-2-4] Radiation Hardness Evaluations of 65 nm FD-SOI and Bulk processes by Measuring SET Pulse Widths and SEU Rates

E. Sonezaki¹, J. Furuta¹, K. Kobayashi¹ (1.Kyoto Inst. of Tech. (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-2-5L] Charge Pumping Current from Single Si/SiO₂ Interface Traps: Direct Observation of P_b Centers and Fundamental Trap-Counting by the Charge Pumping Method

T. Tsuchiya¹, Y. Ono² (1.Shimane Univ., 2.Univ. of Toyama (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-3-1] A 16nm FinFET CMOS Technology for Mobile SoC and Computing Applications

S.–Y. Wu¹, C.Y. Lin¹, M.C. Chiang¹, J.J. Liaw¹, J.Y. Cheng¹, S.H. Yang¹, C.H. Yao¹, T.L. Lee¹, W. Chang¹, C.C. Chen¹, M.H. Tsai¹, S.M. Jang¹, K.S. Chen¹, Y. Ku¹ (1.Taiwan Semiconductor Manufacturing Company (Taiwan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-3-2] Detailed Analysis of Minimum Operation Voltage (V_min) of Extraordinarily Unstable Cells in Fully Depleted Silicon-on-Thin-BOX (SOTB) 6T-SRAM

T. Mizutani¹, Y. Yamamoto², H. Makiyama², T. Yamashita², H. Oda², S. Kamohara², N. Sugii², T. Hiramoto¹ (1.Univ. of Tokyo, 2.LEAP (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-3-3] Comparison and Statistical Analysis of Four Write Stability Metrics in Bulk CMOS SRAM Cells

H. Qiu¹, T. Mizutani¹, T. Saraya¹, T. Hiramoto¹ (1.Univ. of Tokyo (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-3-4] High Reliability SRAM Development for 40nm Embedded Spilt Gate-MONOS

S. Okamoto¹, K. Maekawa², Y. Kawashima¹, K. Shiba², H. Sugiyama¹, M. Inoue¹, A. Nishida¹ (1.Renesas Electronics Corp., 2.Renesas Semiconductor Manufacturing Co., Ltd. (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

[J-3-5L] The Guideline of Si/SiGe Hetero-Junction Design in Parallel Plate Style TFETs (PP-TFETs) for Si CMOS Platform Implementation

M. Goto¹, Y. Kondo¹, Y. Morita², S. Migita², A. Hokazono¹, H. Ota², M. Masahara², S. Kawanaka¹ (1.Toshiba Corp., 2.GNC, AIST (Japan))

2014 International Conference on Solid State Devices and Materials |PDF Download

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