[F-1-4] Novel 2step Writing Method for STT-RAM to Improve Switching Probability and Write Speed

F. Iga¹、Y. Suzuki¹、T. Ohsawa¹、S. Ikeda¹、T. Hanyu¹、H. Ohno¹、T. Endoh¹ (1.Tohoku Univ. , Japan)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-2-1] An Overview of Embedded Ferroelectric Memory Technology

K. R. Udayakumar¹、T. S. Moise¹、S. R. Summerfelt¹、J. Rodriguez¹、M. Ball¹、L. Wang¹、H. McAdams¹、S. Madan¹ (1.Texas Instruments Inc. , USA)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-2-2] Data Disturbance-free NAND-type Ferroelectric-gate Thin Film Transistor Array using Solution-processed ITO and Stacked (BLT/PZT) Gate Insulator

B. N. Q. Trinh¹、T. Miyasako¹、T. Kaneda¹、P. V. Thanh²、P. T. Tue²、E. Tokumitsu^1,3、T. Shimoda^1,2 (1.JST、2.JAIST、3.Tokyo Tech , Japan)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-2-3] Process Development of ALD-Rutile-TiO₂/Ru(O_x) for DRAM MIMcap Application and its Leakage Mechanism Analysis

K. Tomida¹、M. Popovici¹、J. Swerts¹、W. C. Wang²、B. Kaczer¹、M. A. Pawlak¹、S. Van Elshocht¹、M. S. Kim¹、I. Debusschere¹、V. V. Afanasiev²、L. Altimime¹、J. A. Kittl¹ (1.imec、2.Catholic Univ. of Leuven , Belgium)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-2-4] Optimization and Variation Studies of BJT-based Ultra Thin Body Capacitorless DRAM Cell

M. H. Cho¹、C. Shin¹、T. J. K. Liu¹ (1.UC, Berkeley , USA)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-2-5] A Compact Half Select Disturb Free SRAM Cell with Stacked Vertical MOSFET

H. Na^1,2、T. Endoh^1,2 (1.Tohoku Univ.、2.CREST-JST , Japan)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-3-1] First 64kb Ferroelectric-NAND Flash Memory Array with 7.5 V Program, 10⁸ Endurance and Long Data Retention

X. Zhang¹、M. Takahashi¹、K. Takeuchi²、S. Sakai¹ (1.Natl Inst. Adv. Ind. Sci. and Tech.、2.Univ. of Tokyo , Japan)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-3-2] Assessment of Erase-Verify Function in NAND Arrays with Charge-Based Capacitance Measurement

L. H. Chong¹、Y. W. Chang¹、K. F. Chen¹、Y. J. Chen¹、S. H. Ku¹、N. K. Zous¹、I. J. Huang¹、T. T. Han¹、M. S. Chen¹、W. P. Lu¹、K. C. Chen¹、C. Y. Lu¹ (1.Macronix Int. Co., Ltd. , Taiwan)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-3-3] Disturb-free 3D vertical FG NAND with Separated-Sidewall Control Gate

M. S. Seo^1,2、T. Endoh^1,2 (1.Tohoku Univ.、2.CREST-JST , Japan)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

[F-4-1] A Zero Additional Process to Standard CMOS, 8F², Scalable Embedded Flash Memory with Drain-side Assisted Erase Scheme

Y. Shinozuka¹、K. Miyaji¹、K. Takeuchi¹ (1.Univ. of Tokyo , Japan)

2011 International Conference on Solid State Devices and Materials |PDF ダウンロード

741件中(201 - 210)

« 前へ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
次へ »

▲