Oral presentation

[17p-A16-1~14] 13.4 Devices/Integration Technologies

Wed. Sep 17, 2014 2:00 PM - 5:45 PM A16 (E307)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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2:00 PM - 2:15 PM

[17p-A16-1] Observation of the spin blockade in a silicon double quantum dot using a charge sensor

^○Horibe Kosuke¹, Tetsuo Kodera^2,3, Shunri Oda¹ (QNERC, Tokyo Tech.¹, Dept. of Phys. Elecreron.², NanoQuine, Univ. of Tokyo³)

2:15 PM - 2:30 PM

[17p-A16-2] Observation of the electrostatic coupling between two silicon double quantum dots

^○Yi Lu¹, Kousuke Horibe¹, Tetsuo Kodera², Shunri Oda¹ (QNERC, Tokyo Tech¹, Dept. of Phys. Electron, Tokyo Tech²)

2:30 PM - 2:45 PM

[17p-A16-3] Creation of High functionality of three-terminal Nanodot Array device (2)

^○Isamu Yoshioka¹, Takafumi Uchida¹, Hikaru Satoh¹, Masashi Arita¹, Akira Fujiwara², Yasuo Takahashi¹ (IST. Hokkaido Univ.¹, NTT Basic Research Labs.²)

2:45 PM - 3:00 PM

[17p-A16-4] Classification of excited states in Si single-electron transistor

^○Hikaru Satoh¹, Takafumi Uchida¹, Isamu Yoshioka¹, Masashi Arita¹, Akira Fujiwara², Yasuo Takahashi¹ (IST. Hokkaido Univ.¹, NTT Basic Research Labs.²)

3:00 PM - 3:15 PM

[17p-A16-5] Si high-speed single-hole transfer devices

^○Gento Yamahata¹, Akira Fujiwara¹ (NTT Basic Research Labs.¹)

3:15 PM - 3:30 PM

△ [17p-A16-6] Suppression of thermal noise by feedback control using single electron detection

^○Kensaku Chida¹, Katsuhiko Nishiguchi¹, Gento Yamahata¹, Akira Fujiwara¹ (NTT BRL¹)

3:30 PM - 3:45 PM

[17p-A16-7] Defect-assisted single-electron transport in short-channel tunnel field-effect transistor

^○Keiji Ono¹, Takahiro Mori², Satoshi Moriyama³ (RIKEN¹, AIST², NIMS³)

3:45 PM - 4:00 PM

[17p-A16-8] On the short channel effects of tunnel FETs

^○Koichi Fukuda¹, Takahiro Mori¹, Wataru Mizubayashi¹, Yukinori Morita¹, Meishoku Masahara¹, Tetsuji Yasuda¹, Shinji Migita¹, Hiroyuki Ota¹ (AIST¹)

4:00 PM - 4:15 PM

[17p-A16-9] Improvement of Epitaxial Channel Quality and Its Impact to Tunnel FET Performances

^○Yukinori Morita¹, Takahiro Mori¹, Shinji Migita¹, Wataru Mizubayashi¹, Koichi Fukuda¹, Takashi Matsukawa¹, Kazuhiko Endo¹, Shin-ichi O'uchi¹, Yongxun Liu¹, Meishoku Masahara¹, Hiroyuki Ota¹ (AIST¹)

Break 16:15～16:30 （4:15 PM - 4:30 PM）

4:30 PM - 4:45 PM

[17p-A16-10] Fabrication and Characterization of 3D Fin-Channel MANOS Type Flash Memory

^○Yongxun Liu¹, Toshihide Nabatame², Takashi Matsukawa¹, Kazuhiko Endo¹, Shinichi Ouchi¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Wataru Mizubayashi¹, Yukinori Morita¹, Shinji Migita¹, Hiroyuki Ota¹, Toyohiro Chikyow², Meishoku Masahara¹ (AIST¹, NIMS²)

4:45 PM - 5:00 PM

△ [17p-A16-11] Metal nanoparticle embedded V-groove Junctionless-FET

^○(D)Takahiko Ban¹, mutsunori Uenuma¹, Shinji Migita², Yasuaki Ishikawa¹, Ichiro Yamashita¹, Yukiharu Uraoka¹ (NAIST¹, AIST²)

5:00 PM - 5:15 PM

[17p-A16-12] Oxide Thickness Dependence of Resistive Switching Characteristics for HfOx based ReRAM Device

^○Daisuke Ito¹, shintaro Otsuka¹, Yoshifumi Hamada¹, Tomohiro Shimizu¹, Syousou Shingubara¹ (Kansai Univ.¹)

5:15 PM - 5:30 PM

[17p-A16-13] Formation of ferromagnetic conductive filament in Ni/HfO₂/Pt resistive switching memory

^○Shintaro Otsuka¹, Yoshifumi Hamada¹, Daisuke Ito¹, Tomohiro shimizu¹, Shoso Shingubara¹ (Kansai Univ.¹)

5:30 PM - 5:45 PM

[17p-A16-14] Conductive Filament in the Early Switching Stage of Cu/MoOx/TiN ReRAM

^○Masashi Arita¹, Yuuki Ohno¹, Masaki Kudo¹, Yasuo Takahashi¹ (Hokkaido Univ.¹)

Poster presentation

[17a-PA3-1~7] 13.4 Devices/Integration Technologies

Wed. Sep 17, 2014 9:30 AM - 11:30 AM PA3 (Gymnasium1)

ポスター掲示時間9:30～11:30(PA3会場)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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9:30 AM - 11:30 AM

[17a-PA3-1] Temperature Dependence of Subthreshold Slope Characteristics of IET-assisted TFETs

^○Takahiro Mori¹, Yukinori Morita¹, Noriyuki Miyata¹, Shinji Migita¹, Koichi Fukuda¹, Meishoku Masahara¹, Tetsuhi Yasuda¹, Hiroyuki Ota¹ (AIST¹)

9:30 AM - 11:30 AM

▲ [17a-PA3-2] Ge/Si Hetero-Junction TFETs with In-situ Boron-Doped Ge-Source

^○Minsoo Kim^1,2, Yuki Wakabayashi¹, Ryosho Nakane¹, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (The University of Tokyo¹, JST-CREST²)

9:30 AM - 11:30 AM

[17a-PA3-3] Change of hysteresis characteristics by the high-speed and pulse measurement on Super Steep Cut Off SOI Device

^○Yosuke Kuramoto¹, Jiro Ida¹, Yasuo Arai² (Kanazawa Institute of technology¹, KEK²)

9:30 AM - 11:30 AM

[17a-PA3-4] Demonstration of front-gate GaSb-OI p-MOSFETs on Si wafers fabricated by direct wafer bonding

^○Koichi Nishi^1,2, Masafumi Yokoyama¹, Haruki Yokoyama^2,3, Takuya Hoshi^2,3, Hiroki Sugiyama^2,3, Mitsuru Takenaka^1,2, Shinichi Takagi^1,2 (Univ. of Tokyo¹, JST CREST², NTT Photonics Labs.³)

9:30 AM - 11:30 AM

[17a-PA3-5] Electrical control of potential barrier with Si-SET attached multiple gate electrodes

^○Takafumi Uchida¹, Isamu Yoshioka¹, Hikaru Sato¹, Masashi Arita¹, Akira Fujiwara², Yasuo Takahashi¹ (IST.Hokkaido Univ.¹, NTT Basic Research Labs.²)

9:30 AM - 11:30 AM

[17a-PA3-6] Influences of Surface Roughness and Impurity Scatterings in Junctionless Transistors

^○Masato Ichii¹, Hideaki Tsuchiya^1,3, Yoshinari Kamakura^2,3, Nobuya Mori^2,3, Matsuto Ogawa¹ (Kove Univ.¹, Osaka Univ.², JST CREST³)

9:30 AM - 11:30 AM

▲ [17a-PA3-7] A 2-12 GHz 1 mW 65 nm CMOS Double Pole Eight Throw Switching Matrix

^〇Afreen Azhari, Takumi Sugitani, Kenta Sogo, Takamaro Kikkawa (Research Institute for Nanodevice and Bio Systems, Hiroshima University)

Oral presentation

[18a-A16-1~11] 13.4 Devices/Integration Technologies

Thu. Sep 18, 2014 9:00 AM - 12:00 PM A16 (E307)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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9:00 AM - 9:15 AM

[18a-A16-1] Systematic Statistical Analysis of Characteristics Variability in Fully Depleted Silicon-on-Thin-BOX (SOTB) MOSFETs and Bulk MOSFETs

^○(M1)Katsuhisa Tanaka¹, Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Tomohiro Yamashita², Hidekazu Oda², Shiro Kamohara², Nobuyuki Sugii², Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

9:15 AM - 9:30 AM

[18a-A16-2] Analysis of DIBL fluctuation of FinFET caused by granular work function variation of metal gates

^○Takashi Matsukawa¹, Kouichi Fukuda¹, YongXun Liu¹, Kazuhiko Endo¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Shinichi O'uchi¹, Shinji Migita¹, Wataru Mizubayashi¹, Yukinori Morita¹, Hiroyuki Ota¹, Meishoku Masahara¹ (AIST¹)

9:30 AM - 9:45 AM

[18a-A16-3] Statistical Analysis of Minimum Operation Voltage (V_min) in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells

^○Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Tomohiro Yamashita², Hidekazu Oda², Shiro Kamohara², Nobuyuki Sugii², Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

9:45 AM - 10:00 AM

▲ [18a-A16-4] Analysis of Delay Time Degradation of Ultra-Low Supply Voltage CMOS Circuit Operating in Subthreshold Region

^○(D)Seung-Min Jung¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (IIS¹)

10:00 AM - 10:15 AM

[18a-A16-5] Vt-tuning technology with low variability for SOTB-FinFETs by back-biasing

^○Takashi Matsukawa¹, YongXun Liu¹, Kazuhiko Endo¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Shinichi O'uchi¹, Shinji Migita¹, Yukinori Morita¹, Wataru Mizubayshi¹, Hiroyuki Ota¹, Meishoku Masahara¹ (AIST¹)

10:15 AM - 10:30 AM

△ [18a-A16-6] Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell

^○(M2)Akitsugu Ueda^1,2, Seung-Min Jung¹, Tomoko Mizutani¹, Anil Kumar¹, Takuya Saraya¹, Toshiro Hiramoto¹ (iis Univ of Tokyo¹, Chuo Univ²)

Break 10:30～10:45 （10:30 AM - 10:45 AM）

10:45 AM - 11:00 AM

[18a-A16-7] Statistical Analysis of Random Telegraph Noise (RTN) in Linear Region and Saturation Region in Scaled Bulk Transistors

^○Misumi Kawakami¹, Tomoko Mizutani¹, Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹)

11:00 AM - 11:15 AM

[18a-A16-8] Comparison of Statistical Distribution of Random Telegraph Noise (RTN) in Bulk and SOTB MOSFETs

^○Yuki Komine¹, Tomoko Mizutani¹, Yoshiki Yamamoto², Hideki Makiyama², Tomohiro Yamashita², Hidekazu Oda², Shiro Kamohara², Nobuyuki Sugii², Takuya Saraya¹, Masaharu Kobayashi¹, Toshiro Hiramoto¹ (IIS, Univ. of Tokyo¹, LEAP²)

11:15 AM - 11:30 AM

△ [18a-A16-9] Random Telegraph Noise in Tri-Gate Silicon Nanowire MOSFETs and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability

^○Kensuke Ota¹, Masumi Saitoh¹, Chika Tanaka¹, Daisuke Matsushita¹, Toshinori Numata¹ (Toshiba R&D Center¹)

11:30 AM - 11:45 AM

△ [18a-A16-10] Investigations on Time Constant Variations in Random Telegraph Noise Phenomena and its Underlying Physical Mechanisms

^○Jiezhi Chen¹, Yusuke Higashi¹, Koichi Kato¹, Yuichiro Mitani¹ (Toshiba R&D Center¹)

11:45 AM - 12:00 PM

[18a-A16-11] Observation of Individual Trap by means of Thermally Stimulated Voltage Shift

^○Yoshiki Yonamoto¹ (Hitachi, Ltd., YRL¹)

Oral presentation

[18p-A16-1~14] 13.4 Devices/Integration Technologies

Thu. Sep 18, 2014 1:30 PM - 5:15 PM A16 (E307)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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Lunch 12:00～13:30 （12:00 PM - 1:30 PM）

1:30 PM - 1:45 PM

[18p-A16-1] Time-Domain Multiply-and-Accumulation with a FinFET and nanodisk array structures

^○Yoshiaki Kuramitsu¹, Takashi Tohara¹, Kazuhiko Endo², Seiji Samukawa³, Meishoku Masahara², Takashi Morie¹ (Kyushu Inst.¹, AIST², Tohoku Univ.³)

1:45 PM - 2:00 PM

△ [18p-A16-2] A process technique for combining a FinFET and nanodisk array structures

^○Takashi Tohara¹, Kazuhiko Endo², Yongxun Liu², Makoto Igarashi³, Seiji Samukawa³, Meishoku Masahara², Takashi Morie¹ (Kyushu Inst.¹, AIST², Tohoku Univ.³)

2:00 PM - 2:15 PM

[18p-A16-3] A scaling limit of MOSFETs associated with drain electrode

^○Kenji Natori¹ (Tokyo Tech.¹)

2:15 PM - 2:30 PM

[18p-A16-4] Operation Limit Imposed by Potential Fluctuations due to Random Dopant in JL-FETs

^○(M1)Kazusa Inoue¹, Katsuhisa Yoshida¹, Nobuyuki Sano¹ (Univ. of Tsukuba¹)

2:30 PM - 2:45 PM

[18p-A16-5] Implementation of Self-Image Potential into Nano-Device Simulations

^○(M1)Yosuke Tsuchiya¹, Katsuhisa Yoshida¹, Nobuyuki Sano¹ (Inst. Appl. Phys, Univ.of Tsukuba¹)

2:45 PM - 3:00 PM

[18p-A16-6] Analytic Compact Model of Source-Drain Tunneling Current in Cylindrical Gate-All-Around MOSFET

^○He Cheng^1,3, Shigeyasu Uno^2,3, Kazuo Nakazato¹ (Naogya Univ.¹, Ritsumeikan Univ.², JST CREST³)

3:00 PM - 3:15 PM

△ [18p-A16-7] Atomistic Calculation of Phonon-limited Hole Mobility in Rectangular Cross-sectional Ge Nanowires

^○Hajime Tanaka¹, Seigo Mori¹, Naoya Morioka¹, Jun Suda¹, Tsunenobu Kimoto¹ (Kyoto Univ.¹)

Break 15:15～15:30 （3:15 PM - 3:30 PM）

3:30 PM - 3:45 PM

[18p-A16-8] Experimental Study on 2D-Si Layers for Future Several-nm CMOS(Ⅷ)

^○Yuya Suzuki¹, Yoshiki Nagamine¹, Masahiro Yamanaka¹, Takashi Aoki¹, Tomohisa Mizuno¹, Tatsurou Maeda² (Kanagawadaigaku¹, Sansouken²)

3:45 PM - 4:00 PM

[18p-A16-9] Experimental Study on 2D-Si Layers for Future Several-nm CMOS (IX)

tomohisa mizuno¹, takashi aoki¹, yuuya suzuki¹, ^○yoshiki nagamine¹, toshiyuki samezima² (Kanagawa Univ¹, Toukyounoukou Univ²)

4:00 PM - 4:15 PM

△ [18p-A16-10] Impacts of Orientation and Cross-sectional Shape on Hole Mobility of Si Nanowire MOSFETs

^○Hiroaki Fujihara¹, Naoya Morioka¹, Hajime Tanaka¹, Jun Suda¹, Tsunenobu Kimoto¹ (Kyoto Univ.¹)

4:15 PM - 4:30 PM

▼ [18p-A16-11] Effects of thinning condensation UTB GOI films by additional thermal oxidation on GOI Characteristics

^○WuKang Kim^1,2, Shinichi Takagi^1,2, Mitsuru Takenaka^1,2 (The University of Tokyo¹, JST-CREST²)

4:30 PM - 4:45 PM

[18p-A16-12] Large-scale Ultrathin Ge-on-Insulator wafer Using Epitaxial Lift-Off (ELO) Technique

^○Tatsuro Maeda¹, Eiko Mieda¹, Hiroyuki Ishii¹, Hiroyuku Hattori¹, Taro Itatani¹, Tetsuji Yasuda¹, Yuuichi Kurashima¹, Hideki Takagi¹, Takeshi Aoki², Yugami Jiro³, Taketsugu Yamamoto², Osamu Ichikawa², Takenori Osada², Tomoyuki Takada², Masahiko Hata², Arito Ogawa³, Toshiyuki Kikuchi³, Yasuo Kunii³ (AIST¹, Sumitomo Chemical², Hitachi Kokusai Electric³)

4:45 PM - 5:00 PM

[18p-A16-13] Formation and Electrical Characteristics of MoS₂ Film by High-Temperature Sputtering

^○Kentarou Matsuura¹, Takumi Ohashi¹, Shimpei Yamaguchi¹, Kouhei Suda², Seiya Ishihara², Naomi Sawamoto², Kuniyuki Kakushima¹, Nobuyuki Sugii¹, Akira Nishiyama¹, Yoshinori Kataoka¹, Kenji Natori¹, Kazuo Tsutsui¹, Hiroshi Iwai¹, Atsushi Ogura², Hitoshi Wakabayahi¹ (Tokyo Tech.¹, Meiji Univ.²)

5:00 PM - 5:15 PM

[18p-A16-14] MoS₂ Film Thinning and Electrical Characteristics on High-Temperature Sputtering

^○Takumi Ohashi¹, Shimpei Yamaguchi¹, Kentarou Matsuura¹, Kohei Suda², Seiya Ishihara², Naomi Sawamoto², Kuniyuki Kakushima¹, Nobuyuki Sugii¹, Akira Nishiyama¹, Yoshinori Kataoka¹, Kenji Natori¹, Kazuo Tsutsui¹, Hiroshi Iwai¹, Atsushi Ogura², Hitoshi Wakabayahi¹ (Tokyo Tech.¹, Meiji Univ.²)

Sessions

13. Semiconductors A (Silicon) » 13.4 Devices/Integration Technologies

[17p-A16-1~14] 13.4 Devices/Integration Technologies

△ [17p-A16-6] Suppression of thermal noise by feedback control using single electron detection

△ [17p-A16-11] Metal nanoparticle embedded V-groove Junctionless-FET

[17a-PA3-1~7] 13.4 Devices/Integration Technologies

▲ [17a-PA3-2] Ge/Si Hetero-Junction TFETs with In-situ Boron-Doped Ge-Source

▲ [17a-PA3-7] A 2-12 GHz 1 mW 65 nm CMOS Double Pole Eight Throw Switching Matrix

[18a-A16-1~11] 13.4 Devices/Integration Technologies

▲ [18a-A16-4] Analysis of Delay Time Degradation of Ultra-Low Supply Voltage CMOS Circuit Operating in Subthreshold Region

△ [18a-A16-6] Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell

△ [18a-A16-9] Random Telegraph Noise in Tri-Gate Silicon Nanowire MOSFETs and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability

△ [18a-A16-10] Investigations on Time Constant Variations in Random Telegraph Noise Phenomena and its Underlying Physical Mechanisms

[18p-A16-1~14] 13.4 Devices/Integration Technologies

△ [18p-A16-2] A process technique for combining a FinFET and nanodisk array structures

△ [18p-A16-7] Atomistic Calculation of Phonon-limited Hole Mobility in Rectangular Cross-sectional Ge Nanowires

△ [18p-A16-10] Impacts of Orientation and Cross-sectional Shape on Hole Mobility of Si Nanowire MOSFETs

▼ [18p-A16-11] Effects of thinning condensation UTB GOI films by additional thermal oxidation on GOI Characteristics